Hello，
One customer used ADS3683 and wanted to configure the Decimation Bypass, 1-wire, 16bit mode, below is the configuration, but the FCLK duty cycle is not 50%.
I found the 0x20~x022 has no problem and 0x1B =0x88, I wonder why the FCLK is abnormal. Please help to analyze:
// 011 0 1 100 -- 0x6c -- 1-wire
write_reg(fd, 0x07, 0x6c);
printf("reg 0x%02x = 0x%02x\n", 0x07, read_reg(fd, 0x07));
// load e-fuse
write_reg(fd, 0x13, 0x01);
usleep(2000);
write_reg(fd, 0x13, 0x00);
usleep(2000);
// configure FCLK
// Decimation Bypass
// 0 00 0 000 0
write_reg(fd, 0x19, 0x00);
printf("reg 0x%02x = 0x%02x\n", 0x19, read_reg(fd, 0x19));
// Decimation Bypass
// 1 0 001 000 -- 0x88, 16bit
write_reg(fd, 0x1B, 0x88);
printf("reg 0x%02x = 0x%02x\n", 0x1B, read_reg(fd, 0x1B));
// FCLK
// 0x0FF000, 16bit
write_reg(fd, 0x22, 0x0F);
write_reg(fd, 0x21, 0xF0);
write_reg(fd, 0x20, 0x00);
printf("reg 0x%02x%02x%02x = 0x%02x%02x%02x\n", 0x22, 0x21, 0x20, read_reg(fd, 0x22), read_reg(fd, 0x21), read_reg(fd, 0x20));
write_reg(fd, 0x24, 0x00);
printf("reg 0x%02x = 0x%02x\n", 0x24, read_reg(fd, 0x24));
write_reg(fd, 0x25, 0x00);
printf("reg 0x%02x = 0x%02x\n", 0x25, read_reg(fd, 0x25));
The readback value is
And the FCLK curve is as this:
Best regards
Kailyn
