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ADC3683: FCLK duty cycle is abnormal

Part Number: ADC3683

Hello,

One customer used ADS3683 and wanted to configure the Decimation Bypass, 1-wire, 16bit mode, below is the configuration, but the FCLK duty cycle is not 50%.

I found the 0x20~x022 has no problem and 0x1B =0x88, I wonder why the FCLK is abnormal. Please help to analyze:

// 011 0 1 100 -- 0x6c -- 1-wire
write_reg(fd, 0x07, 0x6c);
printf("reg 0x%02x = 0x%02x\n", 0x07, read_reg(fd, 0x07));

// load e-fuse
write_reg(fd, 0x13, 0x01);
usleep(2000);
write_reg(fd, 0x13, 0x00);
usleep(2000);

// configure FCLK
// Decimation Bypass
// 0 00 0 000 0
write_reg(fd, 0x19, 0x00);
printf("reg 0x%02x = 0x%02x\n", 0x19, read_reg(fd, 0x19));

// Decimation Bypass
// 1 0 001 000 -- 0x88, 16bit
write_reg(fd, 0x1B, 0x88);
printf("reg 0x%02x = 0x%02x\n", 0x1B, read_reg(fd, 0x1B));

// FCLK
// 0x0FF000, 16bit
write_reg(fd, 0x22, 0x0F);
write_reg(fd, 0x21, 0xF0);
write_reg(fd, 0x20, 0x00);

printf("reg 0x%02x%02x%02x = 0x%02x%02x%02x\n", 0x22, 0x21, 0x20, read_reg(fd, 0x22), read_reg(fd, 0x21), read_reg(fd, 0x20));


write_reg(fd, 0x24, 0x00);
printf("reg 0x%02x = 0x%02x\n", 0x24, read_reg(fd, 0x24));

write_reg(fd, 0x25, 0x00);
printf("reg 0x%02x = 0x%02x\n", 0x25, read_reg(fd, 0x25));

The readback value is

And the FCLK curve is as this:

Best regards

Kailyn

  • Hi Kailyn,

    I will verify the reg writes today.

    Is the customer using TI EVM or are they using the part in their own setup?

    Can you please verify the ADC clock rate and what is supplying it?

    Best regards,

    Drew

  • Hi Kailyn,

    Customer is using bypass correct? In this case, registers 0x20, 0x21, and 0x22 should not be altered.

    Per this registers description:

    "These bits can adjust the duty cycle of the FCLK. In decimation bypass mode the FCLK pattern gets adjusted automatically for the different output resolutions. Table 8-30 shows the proper FCLK pattern values for 1-wire and 1/2-wire in real/complex decimation."

    Can the customer retake this measurement leaving these registers to their default value?

    Best regards,
    Drew

  • Kailyn,

    I got some time to set this up today. I found that the FCLK output looks normal for the register writes you provided. Register 0x21 default is 0xFC but I didn't see a difference on the scope. I have attached an image of the FCLK on our EVM.

    FCLK is somewhat dependent on CLK and DCLK. Can you please verify what frequencies the customer is using for the clocks?

    Regards,

    Drew

  • Hi Drew,

    Thank you very  much for your reply. I will confirm to the customer. 

    Best regards

    Kailyn