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DAC39J82EVM: How to use DAC3xJ8x GUI V1.3 with DAC39J82EVM and ZCU102

Juan Escobedo
Prodigy 40 points
Part Number: DAC39J82EVM

Hello.

We are using a ZCU102 and DAC39J82EVM as a development platform for a project but we are not sure about what do some of the parameters mean.

First, in the Clocking tab of the DAC3xJ8x controls: What is the difference between DACCLK, JESDCLK and SERDER CLK? Our DACCLK is 2.4576GHz and we are sending 307.2MSPS on 2 lanes with lane speed of 6.144Gbps.

We also observe the SYNC signal goes low when we select either "Code synchronization error", "8b/10b not-in-table code error", or "8b/10b disparity error" from the SYNC request setting. 

Is this more likely due to a misconfiguration on the FPGA side or the DAC side?

Thanks beforehand,

Juan

  • 0
    TI__Mastermind 23760 points

    Hi Juan,

    The different clocks can be ignored as they are internal to the DAC. These settings were made available since they may change due to operating mode, however once set for LMFS and interpolation, they will not need to be changed again.

    Does SYNCb ever rise at all? In other words, is the link always stuck in CGS/ILAS or does it come up sometimes and is often being re-sync due to these error masks you have selected? Can you post the errors from the DAC alarms page? Is this using xilinx JESD IP or TI-JESD204-IP?

    Thanks, Chase