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ADS54J60EVM: ADS54J60EVM ZC706 vivado block diagram

shambhuling d
Prodigy 80 points
Part Number: ADS54J60EVM
Other Parts Discussed in Thread: ADS54J60

Dear Amit,

We are now porting this project into custom board  with the help of our interface logic. So, in this regard we need to edit following file, but the file is read only.

vivado_run/project_1/project_1.gen/sources_1/bd/adc54j60_lmfs_4244_bd/synth/adc54j60_lmfs_4244_bd.v

(Block diagram design based VIvado project was shared by you)

   

   Kindly, provide the editable file, to enable us to port the code at the earliest.

  Regards,

Shambhuling D

(Manager,D&E/MS)

 

  • 0
    TI__Intellectual 1441 points

    Hi Shambhuling,

    We are looking into this. I believe we should have something by end of week or early next week. Thanks!

    Fadi

  • 0 in reply to Fadi Matloob
    TI__Genius 17831 points

    Hi Shambhuling,

    Can you share what changes need to be made in order to port this design to your custom board? It should be possible to import the block design into your project and make the necessary changes in Vivado, such as pin mapping.

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Prodigy 80 points

    Hi David Chaparro

    We are using 4 ADC IC's as per our custom board, for 1 ADC IC was working fine. We wanted to make changes as per our custom board.

    In this block diagram TCL scripting is used, now we don't want to run this design based on TCL scripting. We need without TCL script. So please ensure that our design will work without TCL Script.

    In this design rx_samples is 256 bit and it is split into 16bit of 16 channels. But in ADS54j60 only 2 channel are there, for one channel of ADC 16 bit of 8 channel data is receiving parallelly. So i wanted to know why 16bit of 8 channel?

    So i wanted to know how many samples will get at one clock.

    Regards,

    Shambhuling

  • 0 in reply to shambhuling d
    TI__Genius 17831 points

    Hi Shambhuling,

    Are you referring to the TCL script that is used to control the reset signals (master_reset_n and rx_sync_reset) and export data? If so then in your design you can simply remove these signals from the VIO and have them controlled by your custom FW. For the data you can remove the ILA and take the ADC data to your custom processing logic.  

    In regards to the number of samples being captured, the reason that we are capturing 8 samples from both channels is because of the LMFS and lane_data_width in the FPGA. For the LMFS 42440 we are capturing 4 samples every frame, 32 bit width, and with the LaneDataWidth set to 64 bits we capture two of these frames and send out the data, which corresponds to 8 samples for each channel.

    Regards,

    David Chaparro