It has relationship with this issue: https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1309747/tms320f28388d-emif-configuration-of-the-oe-wen-cs
I want to ask you, on basis what I wrote in that thread, what would happen in the Byte Parallel communication with the ADC if I want to read a Channel A conversion if I put up the CS after the first 8 bit reading and then pulling it down. I will show you in the picture:
It would be a problem if any time I finish a 8-bit reading (RD high) I deactivate the CS and then put them low to read the next 8-bit reading of the same conversion result?
The same I would like to ask you with the writing register:
I could put up the Chip Select between the two 8-bit frames of a complete 16-bit frame??
