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ADC3662: DDC use with output sampling rate higher than image frequency.

Part Number: ADC3662

Dear TI.

We are testing a board with the ADC3662 on it configured to use the internal DDC.

The system works with a fixed sampling frequency, but the carrier frequency can be different.

When the low frequency carrier is used, the resulting image frequency fits into the output bandwidth.

When we use a high frequency carrier there are no problems but when the low frequency carrier is used it seems that some kind of saturation is happening.

If we disable the 6dB gain into the ADC, the issue seems to disappear, but we are afraid to leave some resolution behind.

We are still investigating the issue, but we'd like an advise if we are doing something wrong.

Thanks and best regards.

Antonio

  • Hi Antonio,

    Can you provide info regarding the signal? Is the device sampling at 25MSPS? What is the NCO/carrier set to when this saturation occurs? Is it in the range of 100kHz, 1MHz, etc?

    Thanks, Chase

  • Dear Chase,

    The adc is sampling at about 16Msps and the carrier is between 50khz and 100khz. The NCO is set at the carrier frequency and downconverting by a factor of 32, so the 2f component arrives to our FPGA.

    I was not able to get the raw data from the adc yet, but we see that after the downconversion into the FPGA, increasing the input signal at a certain point the output I and Q do not increase linearly with the input signal amplitude .

    I was wondering if having the 2f in the output bandwidth of the adc can lead to unwanted behaviours.

    Thanks

  • I reviewed the math, and I think everything is working fine.

    If the carrier is not rejected by the integrated filter the 6dB gain cannot be used because the carrier needs extra range to be represented.

    Enabling it causes the output to not being able to represent correctly the signal and causes the issue.