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ADS8332: Timing diagram for auto sampling using SSCLK as the clock

David Fishelzon
Prodigy 20 points
Part Number: ADS8332


Hi.

Since one conversion takes 18 + 3 = 21 CCLKs 

and to get 21 CCLKs we need to have *2 = 44 SCLKs  per conversion.

and to read the data from the last conversion I need only 16 + 4 = 20 SCLKs

what is the best practice for reading the data?

Do you have a "recommended" Timing diagram?

Thank you.

David.

  • 0
    TI__Guru 67096 points

    Hi David,

    Can you elaborate on how many devices and channels you need to measure? Do you need to cycle through all channels or are you capturing continuous data from a single channel? This will help me recommend the best conversion mode and channel section mode.

    In Auto-Trigger Mode, data can be read from the device after the EOC pin goes low. Simply take /CS low to enable the interface and launch the MSB, and send the minimum number of SCLKs necessary to read all 16 data bits plus the 3 TAG bits, if enabled. When SCLK is used to generate CCLK, there will inherently be more SCLK periods than necessary to read the ADS8332 conversion data. SDO will continue to output zeroes until the end of the frame when /CS returns high.

    Regards,

    Ryan

  • 0 in reply to Ryan Andrews
    TI__Guru 67096 points

    Just to add on to my previous post - Figure 43 shows a comparison between reading conversion results during sampling vs. during conversion. If data are read during the conversion time (EOC = low), the results will correspond to the previous sample, meaning there will be a one-cycle latency. If data are read during the sampling time (EOC = high), the results will correspond to the most recent sample, which maximizes your overall throughput.

    Regards,

    Ryan

  • 0 in reply to Ryan Andrews
    Prodigy 20 points

    I will read 1 channel only - in 300Ksps

    Configuration setting:

        Auto-Trigger Mode & selecting the channel & Tag mode off

    reading will do:

        300Ksps * 21 * 2 = 12.6 MHz SCL clock continuously while doing the following on rising edge -

    1) wait for the EOC = 1

    2) CS = 0

    3) 16 SCLKs:
        from SDO read MSB - LSB 
        to      SDI  write 0xD000

    4) CS = 1
        loop to step 1

    conversion takes 21 CCLKs - so that is 42 SCLKs

    In step 1 expect to be for about 24 SCLKs

    another SCLK in step 2

    16 SCLKs in step 3 & last SCLK in step 4

    step 1 + step 2 + step 3 + step 4 = 24 + 1 + 16 + 1 = 42 SCLKs

    Does this make sense?

    Thank you

    David.

  • 0 in reply to David Fishelzon
    Prodigy 20 points

    Page 13 figure 2 in the data sheet:

    figure 2 page 13

    is convert is "1" - do I need to drive it in auto mode?

    The diagram shows SCLK - but the 21 conversion clocks arrow refers to CCLK?

    Can you please explain this diagram?

  • +1 in reply to David Fishelzon
    TI__Guru 67096 points

    Hi David,

    Apologies for the delay. In Figure 2, /CONVST can be held constant to either a high or low value since this signal is not used in Auto-Trigger Mode.

    You are correct that the diagram defines the cycle period as 21 CCLKS, which is equivalent to 42 SCLKs in your setup.

    Yes your sequence in the previous post makes sense. You mentioned waiting for EOC = 1 - keep in mind that EOC is an active-low signal by default, so the polarity must be changed when configuring the other device settings (i.e. Manual channel select, Auto-trigger, 500 kSPS ("21 CCLKs"), and TAG disabled are also not defaults).

    Does this help?

    Regards,

    Ryan

  • +1 in reply to Ryan Andrews
    Prodigy 20 points

    CFR SDI BIT

    D11 - Manual channel select enabled. = 0
    D10 - Conversion clock (CCLK) = SCLK / 2 = 0
    D9   - Auto-Trigger: = 0 
    D8   - 500kSPS (21 CCLKs) = 0

    D7   - EOC/INT active high = 0
    D6   - Pin used as EOC = 1
    D5   - Pin 10 is used as EOC/INT output = 1
    D4   - Auto-NAP Power-Down mode disabled = 1 

    D3   - Nap Power-Down disabled = 1
    D2   - Deep Power-Down disabled = 1
    D1   - TAG bit output disabled = 0
    D0   - Normal operation = 1

    CFR SDI BITs = 0xE07D

    This is what you mean?

  • +1 in reply to David Fishelzon
    Prodigy 20 points

    @Ryan

    you write "so the polarity must be changed when configuring the other device settings"

    Is the above CFR - OK?

    Thank you.

    David.

  • 0 in reply to David Fishelzon
    TI__Guru 67096 points

    Hi David,

    Yes the device settings above look ok. All I meant to indicate was that "waiting for EOC to go high" would require a register write to change the polarity from the default setting. This can be done simultaneously when writing to the other CFR bits, as you wrote in the previous post.

    Best regards,

    Ryan

  • 0 in reply to Ryan Andrews
    Prodigy 20 points

    Thank you for all the clarifications!
    I have one more issue I am unable to resolve from the data sheet.

    Out of the 21 CCLKs used for conversion - EOC is active in 3( = 21 - 18) OR 5( = 21 - 16) ?

    Thank you.

    David.

  • 0 in reply to David Fishelzon
    TI__Guru 67096 points

    Hi David, 

    If you're operating at full speed with TAG bits enabled, then I believe you are correct. But some of the dependencies that determine how long EOC goes high are not a function of CCLK but rather fixed setup and hold times based on design (i.e. t(H2) "EOC high to /CS low" is a 20 ns min spec). Also, if you are not reading the TAG bits, then you can return /CS high sooner and leave EOC low for longer before the next conversion.

    Regards,

    Ryan

  • 0 in reply to Ryan Andrews
    Prodigy 20 points

    I do not plan to use TAG bits - look at my CFR SDI BITs = 0xE07D...
    That means I can get less then 21 CCLKs per conversion?

    20ns in "300Ksps * 21 * 2 = 12.6 MHz SCL clock" is approx. 80ns for a single state - not very close... 
    The state machine cannot violate timing as I see it - do you agree?

  • 0 in reply to David Fishelzon
    Prodigy 20 points

     I can get less then 21 CCLKs per conversion?