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Original question:

AFE5818: AFE5818 received data error

AFE5832: Data receiving error in test mode

wupang17
Prodigy 65 points
Other Parts Discussed in Thread: AFE5832, AFE5832LP

Engineer of AFE5832:
I recently encountered two problems when debugging the AFE5832 chip.
Question 1: The TX_TRIG signal seems to be invalid, because I used the AFE chip to receive 32 signals, the first 16 channel signal and the last 16 channel signal can not be synchronized, they have a fixed misalignment. What should I do to ensure that the TX_TRIG signal is valid?
Question 2: In the following figure, I use the ramp test mode of AFE5832, but there are some problems with the received channel data, but some channels are completely correct, I can't find the reason.

  • 0
    TI__Expert 4600 points

    Hi, 

    The engineer handling these devices is currently on travel. He will respond to your request next week by 18 Jan. Thank you for your patience. 

    Thanks, 

    Karthik 

  • 0 in reply to Karthik Nagabhushana
    Prodigy 65 points

    Thank you for your reply. I will wait patiently.

  • 0 in reply to wupang17
    TI__Expert 4481 points

    Hi,

    At first cut it looks like LVDS receiver timing related issue. What is your current clock speed? Can you reduce it by half and check if that works? How is your FPGA LVDS receiver IP look like? Does it performs DPA? You can once look in optimizing the FPGA receiver IP to solve this problem.

    Regards,

    Shabbir

  • 0 in reply to Shabbir Amjhera Wala
    Prodigy 65 points

    Hi,

    Thank you for your reply.

    I think what you said is correct, it is a problem of receiving timing, I tried DPA, but did not achieve the purpose of calibration. Can you tell me how to solve this problem using the receiving IP of the FPGA?
    Also, what do you think is the cause of this error with the TX_TRIG signal?

  • 0 in reply to wupang17
    TI__Expert 4481 points

    Hi,

    The LVDS data is latched on the DCLK signal. So ideally data from LVDS data lane should toggle in middle of DCLK. If its not the case then there can be setup/hold issues and can lead to timing failure. You might have multiple phases of DCLK in the FPGA. You can try changing the phase for the channels which are showing abnormal ramp data and see if that helps. 

    Any issue related to TX_TRIG will give synchronization related issues across devices. Since here some channels are only showing an issue, so it cant be related to TX_TRIG.

    Thanks!


    Regards,

    Shabbir

  • 0 in reply to Shabbir Amjhera Wala
    Prodigy 65 points

    I have understood the above question. I'm sorry I have another question.
    When I use the test mode ramp, I can observe that the value of the data received on the host computer increases from 0 to 511. However, when I use the signal generator to generate a 5mhz 100mvpp sinusoidal signal input, the amplitude of the received signal is only about 0-10. And if the input signal is not added, the received echo is only 0-15. These AD samples are too small, much smaller than 512.
    May I ask why this is? I have adjusted the gain size of the LNA PGA, but it still doesn't solve the problem.The following three pictures illustrate the problem. Looking forward to your reply!

  • 0 in reply to wupang17
    TI__Expert 4481 points

    Hi,

    One possibility could be channel mapping. You might be applying signal on channel N but data captured may correspond to adjacent channel. You can see LVDS data for all the channels once. 

    If you are looking at right channel, then signal chain gain may be small. To increase the signal gain, try increasing the LNA gain by using "Programmable Fixed-Gain Mode"

    Thanks!

    Regards,

    Shabbir

  • 0 in reply to Shabbir Amjhera Wala
    Prodigy 65 points

    Hello, thank you for your reply.
    I checked. I didn't mix up the reception channels. The increase in signal gain you mentioned, I have set the gain of LNA to 21dB, PGA to 27dB, and the gain of Programmable Fixed-Gain Mode to 288, but the problem still hasn't been solved.
    Thank you!

  • 0 in reply to Shabbir Amjhera Wala
    Prodigy 65 points

    I'm sorry, I still can't find out why when I use the signal generator to generate a 5MHZ 100mvpp signal to the AFE5832LP chip, the data after AD is only 0-8. Do you know the reason that may cause this result?

  • 0 in reply to wupang17
    TI__Expert 4481 points

    - Can you please confirm which input channel are you applying the input and which LVDS data are you capturing data?

    - It will be good to confirm if signal is reaching to the device input by probing the input as close to device as possible pin on scope.

    - How much current device is consuming for 1.8V and 3.3V?

    Thanks!

    Regards,

    Shabbir