• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 46 subscribers
  • Views 153 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS54J42: JESD zero data output symptom

JH Shin
Mastermind 9105 points
Part Number: ADS54J42

Hello,

My customer encountered an error where the ADS54J42 JESD output data only output zeros.

This symptom occurs approximately once every 100 to 200 resets, and when the symptom occurs, only zero data is received from the FPGA without an error.

Please give us advice on the cause of this symptom.

Please let us know if there is a way to detect the error in the ADC when this symptom occurs.

Thank you.

JH

  • 0
    TI__Intellectual 1391 points

    Hi JH,

    • How are you doing the resets?
    • What FPGA are you using?
    • Can you send a block diagram of the clocking to the ADC and FPGA?
    • Can you send a block diagram of the JESD IP in the FPGA?
    • Is the link up and running when this happens?
      • What is the status of the SYNC~ signal when this occurs?
      • Does the ADC send the proper characters during CGS and ILAS?
      • What is the status of the RX_VALID in the FPGA?
    • Have you observed this on multiple boards?

    Thanks!

    Cheers,

    Fadi