Dear Technical Support Team,
"Figure 9-10. Layout example: top layer of ADC356x/368x EVM".
In "Figure 9-10. Layout example: top layer of ADC356x/368x EVM", PIN14 and PIN37 are connected directly at the TOP layer, and other GNDs (IOGND, etc.) seem to be via VIA.
Can you tell me the reason for the above?
Is it NG to be connected at TOP?
Or is it possible to connect all of them via VIA to Layer2 GND?
Best Regards,
ttd