ADS7953: Datasheet does not specify digital input/output for +VBD = 1.8V

Hi Esteban,

For 1.8V, Vil for the ADS7953 would be 0.36V.  We'll look into getting that updated with the next datasheet revision.

Could you double check that spec? most standards are 0.35*(+VBD) = 0.63V for VIL Max. Just want to make sure that's correct. 

Hi Esteban,

The number I was given for the ADS7953 was 20% of VBD as Vil when running at 1.8V.

Got it. The issue we are having is that we are trying to interface this ADC with a 1.8V JEDEC (JESD8-7A) compliant FPGA and the ADC limits are not meeting this requirement. By any chance, do you know if this ADC is suppose to meet the 1.8V JEDEC (JESD8-7A) standard? 

Just double check that 20% because I was referencing another TI ADC (ADS8686S) and their spec looks more familiar. This part unfortunate won't work for me because it's too big.

Do you know what's input source or sink current for those digital inputs?

Hi Esteban,

I do not believe the ADS7953 was specifically targeted towards the JEDEC standard.  Based on the Vil for 5V and 3V, neither of those are at the 'typical' 30% of VBD either.  I'll ask about the loading conditions.