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ADC08DJ5200RF: Fine gain adjusting of individual banks in single channel mode

Juan Montero
Prodigy 10 points
Part Number: ADC08DJ5200RF

Hello,

I have a ADC08DJ5200RF running on single channel mode and I'm performing a foreground calibration during initialisation. I am noticing a high SNR in the output when I grab a memory export that contains the output of the ADC. If I grab this output and then split it into four interleaved arrays, this should give me four arrays with the output of each individual bank of cores A and B, correct? Here's the pseudocode that does this:

ArrayIterator = 0;
for (u8 i = STARTING_POINT; i <= (END_POINT-4); i+=4)
{
    stADCCoresInfo.ADCABank0[ArrayIterator] = SingleFrame[i];
    stADCCoresInfo.ADCBBank0[ArrayIterator] = SingleFrame[i+1];
    stADCCoresInfo.ADCABank1[ArrayIterator] = SingleFrame[i+2];
    stADCCoresInfo.ADCBBank1[ArrayIterator] = SingleFrame[i+3];
    ArrayIterator++;
}

Is it a correct assumption that splitting the ADC output this way gives me the outputs of the individual banks of cores A and B?

When I plot the values in these arrays, I get something like this:

If I'm splitting the data correctly, each colour in this plot represents an individual bank of each core. Given this, I want to fine tune the gain of each bank so that they're as close as possible to the mean of the selected data segment. This particular signal is programmed in a manner that the highest positive edge is always on the same position, so I'm analysing the segment immediately after.

I am trying to adjust the gain by changing the value of GAIN_A0_FGDES, GAIN_A1_FGDES, GAIN_B0_FGDES and GAIN_B1_FGDES. I am assuming the default value of these registers is 0x10 (since it's not mentioned in the datasheet), which is the middle point between 0x00 and 0x1F, so I'm going up or down from that value depending on the analysed data. However, I'm not noticing any difference when I change the registers, and if I read them back, I get 0x10 every single time, whether I'm reading them before or after writing to them. The datasheet doesn't mention whether something else needs to happen before writing to these registers, so I'm just doing it "on the fly" after foreground calibration has been performed.

Could I get more clarity on how exactly to perform fine gain adjustment?

Thanks in advance

  • 0
    TI__Mastermind 20755 points

    Hi Juan,

    You are performing the right steps to accomplish this. The ADC architecture is inherently interleaved (per ADC core) and then in single channel mode, the ADC cores are both interleaved. This results in the single channel DES mode ADC bank sampling order looking like A0,A1,B0,B1. All of above is to say that you have unwrapped the data accurately.

    You will notice that you have two lines which follow each other very tightly. The blue and green traces represent one ADC core and then red and orange traces represent the other ADC core. Within each core, the two banks are trimmed to match each other during the creation of the device and these are fused into the ROM, this way the two sub-ADC banks match each other by default.

    To override the ROM trim value and manually adjust the fine gain for these banks, there is no special step or previous requirement before you can modify the values in registers 0x354 through 0x357. I would however recommend this is done immediately after foreground calibration (and also prior to JESD EN).

    I have just tested this on hardware in the lab and am able to readback without any issues. See below. On my board, the default value for A0 and A1 are both 0x10 and the default value for B0 and B1 are both 0x01.

    Without modification of 0x354, 0x355:

    With modification of 0x354 = 0x1F, 0x355=0x1F: The result is a slight ripple from ADC core A and ADC core B being mismatched (because default value is when they are 'best' matched during IC testing/trimming).

    With modification of 0x354 = 0x1F, 0x355=0x00: The result is a even worse ripple from ADC core A and ADC core B being mismatched but also banks 0 and 1 within ADC core A not matching.

    The result of these tests is to simply show that these registers do modify the behavior. Do you have any issues reading other register values?

    Thanks, Chase

  • 0 in reply to Chase W
    Prodigy 10 points

    Hi Chase,

    Thank you very much for your detailed reply. Before I try anything, there's something you said that caught my attention:

    Chase W said:
    I would however recommend this is done immediately after foreground calibration (and also prior to JESD EN)

    I certainly haven't been doing this since I didn't see anything like that in the datasheet. I have been writing the trim values after foreground calibration, but this is done after I set JESD_EN to high. The datasheet instructs to perform the steps in the following order:

    Foreground calibration here is triggered by CAL_SOFT_TRIG, correct? if so, how could I write the trim values after foreground calibration and before setting JESD_EN, if a calibration hasn't happened at this point? Hope the question makes sense.

    Kind regards,

    Juan

  • 0 in reply to Juan Montero
    TI__Mastermind 20755 points

    Hi Juan,

    After the link is up, you can do the following:

    • 0x200 0x00 (de-assert JESD_EN)
    • 0x6C 0x00 (de-assert CAL_SOFT_TRIG)
    • 0x6C 0x01 (assert CAL_SOFT_TRIG to perform foreground calibration)
    • perform the writes to registers 0x354-0x357
    • 0x200 0x01 (assert JESD_EN)

    Thanks, Chase

  • 0 in reply to Chase W
    Prodigy 10 points

    Brilliant, thank you very much. Will try this first thing tomorrow morning since it's night time for me just now.

    Regards,

    Juan

  • 0 in reply to Juan Montero
    TI__Mastermind 20755 points

    No problem.

    Also, I am only suggesting this order/sequence because this is how the software works in the lab. And because I had no issues with modifying the fine gain adj registers using that software, it might be worth a shot to see if the sequencing does affect on your end.

    Thanks, Chase