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AMC1306M25: AVDD

Part Number: AMC1306M25

In the d/s, it specifies that the AVDD high side supply voltage is between 3V to 5.5V. yes, we know it's defined on the d/s. however Customer would like to know what is the min. operating voltage that doesn't specify in d/s? is it 2.8V or lower? 

Regards

Brian

  • Hi Brian,

    Yes, the recommended operating high-side supply voltage is 3-5.5V. 

    The absolute maximum ratings specify the high-side supply voltage can be between -0.3-6.5V. Your customer can operate at 2.8V for high-side supply voltage, but since it is outside the recommended operating conditions, we cannot guarantee functional operation. They will not damage the device at 2.8V though. 

    Do they plan to operate at 2.8V for long periods of time?

    Best regards,

    Eva

  • Thanks. 

    I'd like to describe my question more clear. Customer would like to know the AVDD's UVLO threshold. It means that when AVDD of AMC1306 is going down, what threshold voltage is able to shutdown the device and data/CLK output? Thanks. 

    Regards

    Brian

  • Hi Brian,

    Thank you for clarifying your question. The AMC1306M25 does not define a UVLO threshold, but it does have a fail-safe output feature. This ensures an output of a steady-state bitstream of logic 0s if AVDD is missing or a steady-state bitstream of logic 1s if the common-mode voltage exceeds V_CMov defined in the data sheet (AVDD-2).

    Alternatively, if your customer is looking to shut down the device at a specific threshold voltage, they could consider incorporating a comparator to trigger this shutdown. 

    Please let me know what you think or if you have more questions. 

    Best regards,

    Eva

  • Thanks Eva.

    In reality, how come customer asking this question because there's something problem during AVDD power-off with competition device. Customer'd like to know that is there any UVLO threshold of the AVDD or called brown out threshold that without d/s spec? what's the minimum operating voltage of AVDD on this silicon? Is that possible you can offer such threshold value to help customer to clarify issue? Very thanks. 

    and also, what's the threshold voltage during AVDD power off that could trigger fail-safe function and lead to the logic 0s at output bitstream? 

    Regards

    Brian

  • Hi Brian,

    I understand. The undervoltage detection for VDD1 has a large variation and typically there is hysteresis, meaning that the level will vary depending on if the VDD1 voltage is rising or falling.

    For example, for falling VDD1 = 3V -> 0V, under voltage detection may trigger around VDD1 = 2.4V. And for rising VDD1 = 0V -> 3V, under voltage detection may release around VDD1 = 2.7V.  

    While we do not define this parameter precisely for the AMC1306M25, we do define it for the AMC1300B where we would expect to get similar results. See example datasheet values below. 

    The value that should trigger fail-safe AVDD would be if there were no AVDD (0V). 

    Hope this helps.

    Best regards,

    Eva