ADC3541: Internal Register Configuration via SPI

Hi,

I will be able to start looking into this early next week.

Would you be able to share a few more details to help us debug?

It would be helpful to have a block diagram of your setup.

Is the hardware a custom design or TI EVM?

I assume you have a way of capturing data to see that the configuration isn't taking effect? What does that look like?

I look forward to hearing back.

Best regards,

Drew

Hi, thanks for the prompt reply.

FYI, I'm currently using the ADC in my project (custom design). I have 2 ADCs in my design, both are connected to a FPGA. I have an IP in my FPGA which will configure the ADC clock (CLKP and CLKM pin) frequency on the fly to allow variable sampling rate. 

I'm trying to setup the SYNC functionality to synchronize my ADCs at runtime, thus I've tried to configure the PDN/SYNC pin via SPI - register address 0x0E. Initially, I've tried to write 0x60 (register data) to both ADCs simultaneously to issue the SYNC command via SPI write. Although the SYNC command is successfully written to the ADCs (I've verified via SPI read and getting expected register data - 0x60), however I'm not seeing any synchronization effect on both my ADCs.

After seeing the SYNC command via SPI write has no effect on the synchronization, I've tried to write 0x80 to register 0x0E during initialization to enable the physical PDN/SYNC pin to manually fire an external SYNC pulse via the FPGA. However, before proceeding to fire the SYNC pulse, I've tried to verify whether the configuration is successful (SYNC PIN EN) by reading back the register data at address 0x0E, but getting 0x00 instead of 0x80.

Below are the ways I used to captured the data and confirming SYNC is not working:
1) Configuring ADC clock (CLKP and CLKM pin) frequency before starting to sample data from both ADCs
2) Fire SYNC command externally/via SPI write 
3) Sample both the ADC data and plot out to verify on the phase
From the sampled data, both my sample signals produced different phases every time I repeat the steps I mentioned above. For example, my ADC clock is running at 8MHz, and I'm seeing multiple of 45degrees difference between the sampled signals.

For the SPI write/read communication lines, I've tried to probe on the hardware through an oscilloscope and I'm seeing the expected waveforms (24 bits word etc) as mentioned in datasheet section  8.5.2.1 and  8.5.2.2, not to mention I've also fulfilled the timing requirement as mentioned in the datasheet.

Let me know if you need any more infos.

Hi,

This is good information, thank you!

There are a few more things I would like to confirm.

1)Have we proven good data out on each adc individually?

2)Is a hardware reset being performed before configuring the devices?

3)What is the entire set of register writes being performed to intialize the two adc's?

4)How is the the external sync being sent to the pin?

When providing an external SYNC, the following sequence must be followed:

a)Power cycle the device

b)Release the device reset

c)issue the SYNC pulse on the device

d)The (data) phase relation at this point must be stable and repeatable.

Best regards,

Drew

1) Yes, the data output from both ADCs are good.

2) Hardware reset is only being performed during initialization setup.

3) During initialization, these are the set of registers being written:

4) The external SYNC is driven by the FPGA for a period of 64*K clock cycles, where K = 1 as mentioned in datasheet section 8.3.4.5.

Does the device require any reset before issuing the SYNC pulse? Also, when configuring the internal registers via SPI, is there any additional steps that we need to perform?

Hi,

Sorry for the delayed response. The writes all appear correct.

When in the above process is the sync pulse being applied? Before initialization or after?

Could we try writing 0x0E upon power up and performing the sync, and then initializing the part with the remaining register writes?

Best regards,

Drew

Hi,

Just to clarify my last response. That sequence would be power up the device, perform hardware reset, perform software SPI reset (Reg 0x00 and Data 0x01), then write 0x0E and perform the sync pulse, and then finish the remaining register write initialization.

Best regards,

Drew