Multiple DAC7513s on same SPI bus

Hi John,

The /SYNC pin behavior in this part behaves like a /CS. You should be able to use the /SYNC pin to distinguish between which DAC you want to talk to on the SPI bus.

Regards,

Tony Calabria

Tony,

Thanks for your quick reply.  Does this mean that when /SYNC goes high, all other signal pins on the DAC7513 are placed in a high-impedance state?  I just want to make sure that this DAC doesn't load the bus when it isn't being talked to. 

Thanks.

John S.

Hi John,

Generally, high impedance states is what you want when it comes to logic outputs, and not necessarily logic inputs. If you look into a logic input (SCLK, DIN, etc) on a device, you are looking directly into an internal buffer which increases the drive capability of the line. The SCLK line, for example, will be controlling multiple 'places' throughout the chip and that requires some drive strength. You cannot rely solely on the uC to achieve this, so that the device is structured to have an internal buffer. When a /CS or /SYNC is brought high, what usually happens is the internal buffer on the input pins is disabled while the output (DOUT on some chips) is set to high impedance. When the input buffer is disabled, there will still be some impedance effects on the line. These effects will add up as you have more and more items on the SPI bus and is why you cannot always share 100s of items on one SPI bus. If the input lines went high impedance, then they would float between a 'high' and a 'low' enabling and disabling internal circuitry components the entire time.

Now, that description explains how parts are done today. In older parts (like the DAC7513) the logic inputs may not be blocked off and instead the logic inputs travel through the parts. However, the logic code integrated into the device is coded so that the device does not respond to the SCLK and DIN traveling through the lines. This process generally consumes more power which is why the one explained above is more common in newer parts. I would have to track down the designer to see exactly how these inputs were designed.

So, to answer your question - The inputs are not high impedance and there will be some sort of loading effects. How many DACs to do you plan to share on the SPI bus? 

Regards,

-Tony

Tony,

Thanks for your detailed response.  We are planning on using two of these DACs as well as a third IC on the SPI bus.  Based on your explanation, I'm assuming that the loading effects will not be significant enough to cause any communication problems.  Is that correct?

Thanks.

John S.

Heard back and design team says should be fine.

-Tony