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ADC121S021: What is the maximum time from turning CS LOW to 13CLK (conversion complete)?

Part Number: ADC121S021

Hi team,

I think this IC holds when CS goes LOW and performs conversion at 13CLK (HOLD TIME), but what is the maximum hold time?

When I send a clock (16CLK) 30 seconds after setting CS to LOW and look at the data, the value deviates considerably from the expected value.

Best Regards.

Taiichiro Suda
  • P.S.

    I use an ICE from a microcontroller to check a board with multiple devices by manipulating the CS signal.

    When I check the CS a few seconds after operating the CS, some ICs have a large deviation and some have almost no deviation, so I would like to check the upper limit value.

  • Hi Suda-san,

    Thanks for your question. The hold time for this device is 13 SCLK periods after /CS is pulled low. That is the typical time, there isn't really a maximum or minimum. Please note the following regarding holding /CS low:

    Could you please clarify what you mean by "When I send a clock (16CLK) 30 seconds after setting CS to LOW and look at the data, the value deviates considerably from the expected value."? Please note the below highlighted text. 

    Best,

    Samiha

  • Hi Samiha,

    > The hold time for this device is 13 SCLK periods after /CS is pulled low. That is the typical time, there isn't really a maximum or minimum.

    The above is exactly what I want to know.

    I am using ICE to manipulate the microcontroller's registry and check the board. After setting CS to L, manually transmit SCLK at any timing.(SCLK is 1MHz & CS is kept at L)

    It takes several seconds to reach SCLK after setting CS to L, but some ICs have large variations, while others have very little variation.

    However, send SCLK 30 seconds after setting CS to L and check the conversion results, all ICs will have bad results.

    The data sheet has a minimum tSU (CS is set to L until SCLK can be input), but there was no maximum specification.

    (I thought that if I knew the maximum value of tSU, I could find the minimum value of HOLD time along with the minimum value of clock.)

    I think that if the time between holding and converting is long, the error will increase due to leakage current.

    Is there a recommended value for HOLD time (from setting CS to L to 13clk)?

    best regards

    Suda

  • Hi Suda-san,

    Thanks for explaining. You are right, leaving /CS low for too long before applying SCLK will cause the sampling capacitor to discharge due to leakage current, causing incorrect conversion results. A few seconds is a really large duration to leave /CS low before applying SCLK. The maximum time between /CS low and SCLK may be estimated by looking at tCL and tCH. So, when using SCLK=1MHz, it is about 400ns. You may be able to wait as long as 1-2 SCLK periods, but I would recommend staying within 400ns to avoid violating tCL and tCH.

    I hope that helps.

    Best,

    Samiha

  • Hi Samiha,

    Thank you for your answer.

    I understand that I need to start converting as soon as possible after setting up CS.(After more than 10ns (tSU))

    This IC is allowed to clock at a minimum of 25kHz, but is there any gain error data for that?

    The specifications in the data sheet only listed data for 1MHz to 4MHz.

    I thought that if the condition is 25kHz, the specs when Hold time is 0.5s can be understood.

    Best regards,

    Suda

  • Hi Suda-san,

    Could you please clarify what you mean by the IC is allowed to clock at a minimum of 25kHz? The datasheet states the minimum SCLK frequency as 1MHz.

    Best,

    Samiha

  • Hi Samiha,

    Page 4 of the datasheet contains Recommended Operating Conditions.

    According to the above, the device can operate from 0.025MHz.

    If you have spec data at 0.025MHz, please let me know.

    Best regards,

    Suda

  • Hi Suda-san,

    Looks like this may be a typo from when the National Semiconductor datasheets were moved to TI datasheet formatting. The correct ADC121S021 clock frequency range is as listed in section 7.5: 1MHz (min) to 4MHz (max). Thanks for pointing that out, I will request an update.

    Best,

    Samiha

  • Hi Samiha,

    Thank you for confirmation.

    (All relevant parts of the data sheet for the ADCxx1Sxx1 series were from 25kHz, so I thought that there was data that had been tested, even if the device specifications were worse than the specifications listed in the data sheet.)

    Since we are using isolated transmission, I wanted to provide as much leeway as possible.

    However, your company's isolated transmission IC (ISO6472) has good performance and has little delay, so there seems to be no problem.

    I don't have more questions so far.
    I'm looking forward to revising the version of datasheet.

    Thank you for your cooperation.

    Best,

    Suda