DAC714: LSB step settling time of DAC714

Marcos Lam

Part Number: DAC714

DAC714 datasheet is has spec for 1 LSB step settling time of 4us. An associated footprint states that : "(5) For the worst-case Binary Two’s Complement code changes: FFFFH to 0000H and 0000H to FFFFH" the 4us is for simple 1 LSB change step or the worst case of binary Two's complement code changes? Please clarify.

7 months ago

0 Erin Bowrie 7 months ago

TI__Expert 6790 points

Hi Marcos,

4us is the settling time when going between FFFFh to 0000h and vice versa. Since this is two's complement, the output on the DAC when going between FFFFh and 0000h is 1 LSB. As this is the worst case scenario due to how many bits are flipping, all other 1 LSB step settling will be equal to 4us or less.

Thanks,
Erin

0 Marcos Lam 7 months ago in reply to Erin Bowrie

Prodigy 40 points

Above "1 LSB step" is "20V output step" with value of typical 6us and max 10us. If 4us for transition between FFFFh and 0000h, how could the 20V output step has larger settleing time?

I am very confused now. -Marcos

0 Erin Bowrie 7 months ago in reply to Marcos Lam

TI__Expert 6790 points

Hi Marcos,

Since it's two's complement, FFFFh and 0000h are actually very close together for output.

0000h = 0.000000V
FFFFh = -0.000305V

The 20V step will naturally take longer to settle in this case, as you are going from minimum full scale to maximum, ie -10V to 10V. 0000h to FFFFh is only a 0.000305mV step.

Thanks,
Erin

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DAC714: LSB step settling time of DAC714