DAC11001B: Timing diagram

Hi Dietmar,

I'm not sure if this will work. The datasheet says that the data is shifted from the SPI registers into the DAC buffer registers with the rising of SYNC. The Load pin should shift the data from the Buffer registers into the Active registers. I don't believe the Load pin will shift the data from the SPI registers into the Buffer or Active registers. I'll ask a designer if keeping the SYNC pin low and using LDAC instead is feasible.

Thanks,
Erin

Hi Dietmar,

I confirmed with a designer that you cannot keep SYNC low and shift the data into the registers using the LOAD/LDAC pin. Let me know if you have any other questions.

Thanks,
Erin

Hi Erin,

thanks for the quick response.

the data sheet does not say that there are two 32 bit register and that each is controlled by different. The sync looks like a simple gate signal for the clock and not as trigger signal to store a 32 bit in a second register, which is than transferred in to into another register by the falling edge of the load pin.

It would be good if the data sheet contains a circuit diagram how  the digital input, containing 32 bit Shift register - 32 bit Parallel Register loaded with the rising edge  of /sync - 32 bit Parallel Register loaded with the falling edge of /load, is realized. A pictures says more than thousand words. 

In the app note "Demystifying Design Challenges in Ultra-Low Noise, High-Fidelity Waveform Generation Using 20-Bit DAC" you show that the DAC11001B is able to generate a 1kHz sine wave with a 10 kSPS update-rate.

How did the timing diagram locked like for this application?

Kind Regards Dietmar

Hi Dietmar,

It's confusing, but it's described a bit in the LDAC section. First, here's the functional diagram that shows the Buffer register being separated from the DAC register, but it doesn't mention that the trigger is LDAC. 

Section 7.5.3 describes the LDAC function. "The DAC11001B offers both a software and hardware simultaneous update and control function. The DAC double-buffered architecture has been designed so that new data can be entered for the DAC without disturbing the analog output. Data updates can be performed either in synchronous or in asynchronous mode, depending on the status of LDAC-MODE bit (address 02h, B14)." 

If the device is in asynchronous mode, the data will move from the buffer registers to the active registers automatically, without the need for any other input by you. When in synchronous mode, the data will not shift from the buffer registers until LDAC is toggled. In asynchronous mode, you can effectively ignore the LDAC pin.

Timing-wise, I believe the 10 kSPS is within the nominal timeframe of the 30MHz/50MHz SPI frequency of this device. You would use the timing diagram in figure 6.1.

Thanks,
Erin

Hi Erin,

We are gathering more and more good information, but it does not fully answer my questions.

Let's start again with the data sheet, the data sheet speaks of two modes: asynchronous and synchronous, but shows in  "Figure 6-1. Serial Interface Write Timing: Standalone Mode" only one mode without saying which mode is described.

For two different modes I would expect two different timing diagrams. I would be very pleased if you could publish these two timing diagrams.

If we assume the timing you described, then the analog path of the DAC can only be written in burst mode.
32-bit data is shifted into the serial register with 32-bit clock edges. After that Data and clock must be stopped until the data is stored in the DAC in the DAC register.

The needed additional time interval between end of one analog sample and beginning of the next analog sample can be calculated as following Tcsh(SCLK falling edge to SYNC rising edge) 20ns + Tcshigh (SYNC high time) 100ns + Tcss (SYNC falling edge to SCLK falling edge) 36ns = 156ns. Between each 32bit data sample we have to have a gap of 156ns. 

This means that the update frequency of /LDAC is not an even multiple of the shift frequency, as is usually the case with DACs with continuous data and clock signals. In other words, if the DAC runs at 768kHz update rate as described in the datasheet "Figure 6-43. 1-kHz Spectrum vs Frequency" the common shift frequency would be 24.576000MHZ (which is an audio sampling rate). Based on your described timing the real shift frequency has to be higher than 24.576000MHZ to generate a needed time gap between the samples which is higher than 156ns.

Nobody can start a serious design on a "believe". Please verify the information you give here with the designers of the IC.

Please publish the timing diagram used to generate the signal in "Figure 6-43. 1-kHz Spectrum vs Frequency" with an update rate of 768kHz.

Thanks again

Dietmar

Hi Dietmar,

Your correct in that you would need 156ns of gap between each data sample, but this calculation assumes a lower IOVDD and DVDD. Going back to the application note, the team was using 38.4MHz clock frequency, meaning they were operating in the higher input voltage range. Given this, the calculation would become

Tcsh + Tcshigh + Tcss = 10ns + 50ns + 18ns = 78ns. 

Furthermore, if you operate in Asynchronous mode, you will be able to ignore the LDAC pin as the DAC will update automatically on the last edge of SCLK. If you run at the fastest frequency, each set of 32 bits would take around 728ns, giving you a sample rate of over 1Msps. Of course, this is the minimum timeframe for the SPI parameters, so this isn't realistic, but the 768kHz sampling is achievable with the fast SPI clock timing.

Thanks,
Erin