ADS7951: SPI simulation model, HDL

Hi Richard,

Welcome to our e2e forum!  Unfortunately we do not have Verilog or VHDL code to share with you for the ADS7951.  Feel free to send over logic analyzer or O'Scope screen shots of your control lines (/CS, SCLK, SDI, SDO, etc.) and we'd be happy to review that for you.

I've attached a picture of the SPI control lines.  When reset is released, the first SPI transaction is a bit unique.  I see a falling edge on the SPI clock, and then this is followed by a rising edge.  Does that initial falling edge, the one prior to the first rising edge, cause the DO output to change from DO15 => DO14?  Seems like it could affect setup timing in our FPGA as it clocks in the data from the ADC.  Is my interpretation correct about D15 getting bashed by that first falling edge on the SPI clock?

The datasheet shows large propagation delays, for example clock-to-q td2 = 27ns for 3v.  Are these delays what we would expect to see in actual hardware?  What is typical?  Since data is clocked out on the falling edge, it seems capturing on the rising edge may not work at 20 MHz.

Typical is going to be on the order of 12-13ns.