ADC3563: LVDS interface with Lattice FPGA

Jong Kim

Part Number: ADC3563

We've using ADC3563 with two types of FPGA (one is MAX10 and the other is Lattice Certus-NX device).
Interesting thing is interface with MAX10 works well, but some how interface with Lattice device is not working well.

I want to know if we need a special handling with Lattice FPGA especially LVDS signal levels... As we know is Lattice LVDS output peek-to-peek is slightly smaller than MAX10 device (around 50mV range).

Please let me know if you have any recommendations or have a reference design interfacing with Lattice FPGA.

Regards,

Jong

8 months ago

0 Ameet Bagwe 8 months ago

TI__Intellectual 1620 points

Hi Jong,

As long as the signal levels are within the LVDS receiver specs of the FPGA, the interface should work reliably. I am assuming that the timing closure reports are all error free.

Regards,
Ameet

0 Jong Kim 8 months ago

Prodigy 10 points

Hi Ameet,

Thanks for the comment, FPGA side is fine, it looks ADC side is a bit weird.

Sometimes, LVDS DCLK output is not working, but LVDS DCLK input is existing...

Regards,

Jong

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ADC3563: LVDS interface with Lattice FPGA