DAC81404EVM: lack of DAC output control

pawan shirur

Part Number: DAC81404EVM
Other Parts Discussed in Thread: DAC81404

Hello ,

we are trying to configure the DAC81404 on a custom board which has a RFSOC FPGA as controller and data source. We are able to configure and confirm all the registers but we do not have control on the DAC output channels as expected.

the sequence we use to initialize the DAC is as follows. the Value field are the DAC internal register address and data we are writing. for example, register 0x03 is getting written with 0xA84

when we write into broadcast register or individual DAC register channels, we see only either of rail voltages AVDD-AVSS . when we cycle through the code we write into the DAC registers we see that the output switches between positive AVDD and AVSS at only one certain code where we get intermediate value that is non-rail voltage. for all other values below this particular code we see AVSS voltage.

below is example SPI grab on oscilloscope while we write a code x8E6E to DAC register channel 0 register address x10. we are operating below the SPI max clock speeds for IOVDD of 1.8V ( 12MHz) .

channel from A to D which is arranged top to bottom is - CLK, DATA, SYNC, LDAC

we think the SPI communication for all other transactions that we can read back is ok and we do not see any communication issues.

schematic page for DAC.

we are not sure if we have an error in initialization of DAC or something else on board. I would appreciate you help with this issue.

7 months ago

0 Katlynne Jones 7 months ago

TI__Mastermind 30908 points

Hello,

Thanks for your question. Sanjay is reviewing and will get back to you shortly.

best,

Katlynne Jones

0 Sanjay 7 months ago in reply to Katlynne Jones

TI__Intellectual 2830 points

Hi Pawan,

Please confirm -

a. what all components are installed between the nodes DAC_OUTx and DACx for DAC channel A, B and C (for U14).
b. measured voltage on REFIO pin
c. what happens if you don't enable the LDAC mode and just try it out in ASYNC mode (channel D should respond properly).

I will wait for your response, meantime i am going to analyse your amplifier design as that can cause instability for the DACOUT buffer when loop is closed externally.

Thanks,

Sanjay

0 pawan shirur 7 months ago

Prodigy 10 points

Sanjay,

the yellow highlighted filter section for DAC outputs A-C is not installed the orange highlighted components are installed to take DAC output directly out of the PCB. The senseP is connected to DAC out and senseN is grounded . All 4 channels outputs behave the same way. We have tried to cycle code in broadcast as well as individual DAC registers in asyn mode ( we have an option to turn on and off the ldac from spi controller ) . We will try again in async mode on DAC . Just as confirmation In async mode since sync rising pulse is used should the LDAC have rising edge same as synchronous modes ? Or is the LDAC totally ignored by DAC in this mode ?

0 pawan shirur 7 months ago in reply to Sanjay

Prodigy 10 points

The refio measures 2.5V

0 Sanjay 7 months ago in reply to pawan shirur

TI__Intellectual 2830 points

Hi Pawan,

Thanks for the clarification.

In the ASYNC mode, LDAC pin transition and LDAC bit is fully ignored. DACOUT will transition after the SYNC rise edge (with some delay).

Please try these and let me know if helps or not-

a. Provide large delay for each SPI command (min 10 ms). I will suggest to write one SPI read/write command at a time, it's for only debug purpose.
b. Read the SDO data after each SPI command for register address 0x03 (SPI_CONFIG) and 0x09 (DACPWDN). This is to make sure that device is in properer state as expected, all the time.
c. What is cap values for C111, C117 and C122. Make sure they aren't violating the capacitor drive capability as per data sheet.

Thanks,
Sanjay

0 pawan shirur 7 months ago in reply to Sanjay

Prodigy 10 points

Thanks, we will try to implement this manual initialization method. output caps on DAC outputs are also DNI.

0 pawan shirur 7 months ago in reply to Sanjay

Prodigy 10 points

Hello Sanjay,

we are seeing same results with our manual async initialization.

here is a sequence of test ( see attached txt file . the results observed are in CAPS)

1. we did a powerup ( note we do not have DAC_RST in schematic hooked up to logic , so we use the soft reset to check the boot up conditions.

2. we read the boot up state of each of config registers

3. wrote the sequence if initialization manually while in asynchronous mode

4. checked outputs for various DAC codes

5. checked outputs for various broadcast reg. code also

6. we check some key status/config registers in between to check if something changed.

the only anomaly in registers we saw is that the reset or bootup state of Register address 0x2 ( STATUS) is x8 instead of 0000 as per datasheet.

we are not sure what we are doing wrong here. in the boot up sequence

a. do you see anything wrong in our transactions. sample asyn. transaction below where oscilloscopes SPI decoder is also seeing correct transactions

b. is there any requirement. For power sequencing of AVDD and AVSS , DVDD, IOVDD? in our setup the AVSS source is coming from outside the PCB and rest are generated on PCB so the AVSS is not in any sequence of turn on . it could arrive separately while AVDD , DVDD, IOVDD are sequence in that order.

c. could the REFIO - 2.5V connected to other loads cause issue for DAC usage?

d. is there any other reason why the dynamic range of voltage can be limited to just 1-2 bits in the DAC code.?

spi-debug1.txt

//reading back all registers 

dac> read 1
Read 0xa70 from DAC address 0x1.

dac> read 2
Read 0x8 from DAC address 0x2.

dac> read 3
Read 0xaa4 from DAC address 0x3.

dac> read 4
Read 0x4000 from DAC address 0x4.

dac> read 5
Read 0xf from DAC address 0x5.

dac> read 6
Read 0x0 from DAC address 0x6.

dac> read 9
Read 0xffff from DAC address 0x9.

dac> read 0xe
Read 0x0 from DAC address 0xe.


// writing config registers

//enable DAC
dac> write 3 0x0a84
Wrote 0xa84 to DAC address 0x3.
Read 0xa84 from DAC address 0x3.

//check channel status is still off
dac> read 9
Read 0xffff from DAC address 0x9.

//turn off Broadcast for all channels
dac> write 5 0x0
Wrote 0x0 to DAC address 0x5.
Read 0x0 from DAC address 0x5.

//reading key registers for status or any config register changes
dac> read 3
Read 0xa84 from DAC address 0x3.
dac> read 2
Read 0x8 from DAC address 0x2.
dac> read 9
Read 0xffff from DAC address 0x9.

//set range to +/-12V
dac> write 0xa 0xeeee
Wrote 0xeeee to DAC address 0xa.
Cannot readback this address (address is write only)

//reading key registers for status or any config register changes
dac> read 2
Read 0x8 from DAC address 0x2.
dac> read 3
Read 0xa84 from DAC address 0x3.
dac> read 9
Read 0xffff from DAC address 0x9.

//enable all 4 channels 

dac> write 0x9 0xfff0
Wrote 0xfff0 to DAC address 0x9.
Read 0xfff0 from DAC address 0x9.

//AT THIS POINT ALL OUTPUTS GO TO AVSS -11V


//reading key registers for status or any config register changes
dac> read 2
Read 0x8 from DAC address 0x2.
dac> read 3
Read 0xa84 from DAC address 0x3.
dac> read 9
Read 0xfff0 from DAC address 0x9.

//write into DAC channel 0 
dac> write 0x10 0x8000
Wrote 0x8000 to DAC address 0x10.
Cannot readback this address (address is write only)

//OUTPUT STILL AT AVSS 

//reading key registers for status or any config register changes
dac> read 2
Read 0x8 from DAC address 0x2.
dac> read 3
Read 0xa84 from DAC address 0x3.
dac> read 9
Read 0xfff0 from DAC address 0x9.

//write into DAC channel  1
dac> write 0x11 0x8000
Cannot readback this address (address is write only)
dac> read 2           
Read 0x8 from DAC address 0x2.
dac> read 3           
Read 0xa84 from DAC address 0x3.
dac> read 9           
Read 0xfff0 from DAC address 0x9.

//write into DAC channel  2
dac> write 0x12 0x8000
Wrote 0x8000 to DAC address 0x12.
Cannot readback this address (address is write only)
dac> read 2           
Read 0x8 from DAC address 0x2.
dac> read 3           
Read 0xa84 from DAC address 0x3.
dac> read 9
Read 0xfff0 from DAC address 0x9.

//write into DAC channel  3
dac> write 0x13 0x8000
Wrote 0x8000 to DAC address 0x13.


//enable broadcast mode
dac> write 5 0xf
Wrote 0xf to DAC address 0x5.
Read 0xf from DAC address 0x5.
dac> read 2
Read 0x8 from DAC address 0x2.
dac> read 3
Read 0xa84 from DAC address 0x3.
dac> read 9
Read 0xfff0 from DAC address 0x9.

//write into broadacast reg. 

dac> write 0xf 0x0000
Wrote 0x0 to DAC address 0xf.
Cannot readback this address (address is write only)'

//OUTPUT STILL AT AVSS 

dac> write 0xf 0xffff
Wrote 0xffff to DAC address 0xf.
Cannot readback this address (address is write only)

//OUTPUT CHANGES to AVDD

dac> write 0xf 0x8000
Wrote 0x8000 to DAC address 0xf.
Cannot readback this address (address is write only)
//OUTPUT CHANGES to AVSS

dac> read 2
Read 0x8 from DAC address 0x2.
dac> read 3
Read 0xa84 from DAC address 0x3.
dac> read 9 
Read 0xfff0 from DAC address 0x9.
dac> 

//issued soft reset to check condition of registers
dac> write 0xe 0xa
Wrote 0xa to DAC address 0xe.
Read 0x0 from DAC address 0xe.
dac> read 2
Read 0x8 from DAC address 0x2.

//ALL OTHER INDERMEDIATE VALUES GIVE EITHER AVDD TO AVSS. THERE IS ONLY ONE UNIQUE CODE THAT THE OUTPUT FLOATS AND DRIFTS . THIS UNIQUE CODE CHANGES BASED ON DAC RANGE AND IS SLIGHTLY DIFFERENT FOR EACH POWER CYCLE

0 Sanjay 7 months ago in reply to pawan shirur

TI__Intellectual 2830 points

Hi Pawan,

Let's setup a meeting and debug over a call.
Please drop a mail and let me know your convenient time.
Email ID - sk@ti.com

Thanks,

Sanjay

0 pawan shirur 7 months ago in reply to Sanjay

Prodigy 10 points

Hello Sanjay,

thanks for your help outside of this forum.

we were able to fix the issues apart from sense P to DAC out connections ,

the senseN to GND lines components were erroneously not installed so installing that fixed the offset. There is some very small offset per channel but that is less than a 10-12 counts in DAC code .
The DAC channel 4 had the senseP and N pins swapped in our schematic , perhaps a copy of eval board schematic . Once we connected to output and gnd respectively we have control good on that channels.

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DAC81404EVM: lack of DAC output control