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ADC128S102: ADC128S102 Vs ADC128S102-SEP - Minimum Sampling rate difference

Kailasam Mano
Prodigy 30 points
Part Number: ADC128S102

ADC128S102 - is specified from 500ksps to 1Mbps, whereas  ADC128S102-SEP is specified from 50ksps to 1Mbps w.r.to Sampling rate. What is the constraint or Specification difference for using the ADC128S102 IC while using at 50ksps.

We are planning to use ADC128S102 for proto design validation, later it will be replaced by ADC128S102-SEP. Is it ADC128S102 and ADC128S102-SEP is functionally compatible other than -SEP feature.

  • 0
    TI__Expert 6940 points

    Hi Kailasam,

    Thanks for reaching out! In short, yes, for prototyping, the ADC128S102 should electrically perform similarly to the ADC128S102-SEP.

    The difference you are seeing in the datasheet comes from the test conditions. Below, you'll see that the data within the ADC128S102 datasheet was collected with an f_SCLK from 8 MHz to 16 MHz. This results in a f_SAMPLE range of 500 kSPS to 1 MSPS, given the throughput time of 16 SCLK cycles under the AC electrical characteristics of the datasheet.



    Compare that to the test conditions of the ADC128S102-SEP below, which is taken with an f_SCLK from 0.8 MHz to 16 MHz, and resulting in a f_SAMPLE range of 50 kSPS to 1 MSPS, with the same 16 SCLK cycles of throughput time. 


    As you can see, the difference in f_SAMPLE range comes from the different SCLK ranges that the datasheet states. Both parts can operate from 50 kSPS to 1 MSPS. However, the performance of the ADC128S102 is not guaranteed below 500 kSPS as it is with the ADC128S102-SEP.

    Please let me know if you have any further questions.

    Best,
    Joel

  • 0 in reply to Joel Meraz
    Prodigy 30 points

    Hi Joel,

    Thanks for your reply.

    In ADC128S102 Datasheet - AC Electrical Spec, it is also mentioned that Typ Sampling rate is 50kbps and Minimum is 500kbps.

    It looks Sampling rate specification is not clear.

    Also I am not sure, why there is an impact in performance while operating at Low sampling rate?

  • 0 in reply to Kailasam Mano
    TI__Expert 6940 points

    Hi Kailasam,

    I understand that it can seem to be a bit inconsistent when the quoted typical sampling rate is 50 ksps and the "minimum" is 10x higher at 500 ksps. Again, this corresponds to the testing procedure. The ADC128S102 was fully tested only within a clock from 8 MHz to 16 MHz. As each sample takes 16 clock cycles to come out, this will yield a sampling rate range from 500 ksps to 1 Msps. If you drop the clock frequency of your device to "typical" 0.8 MHz, you can achieve the sample rate of 50 ksps.

    I hope this helped clear some of the information up.

    As to your concerns about an impact on performance at lower sample rates, please get back to me if you'd like to clear up exactly what it is that is bringing up this concern.

    Best,
    Joel

  • 0 in reply to Kailasam Mano
    TI__Expert 6940 points

    Hi Kailasam,

    Take a look at this other E2E thread for some more context to your question. I hope it helps!

    Best,
    Joel