ADC12DJ3200EVM: Need support to generate one-shot SYSREF in ADC12DJ3200EVM board.

Hello Krupesh,

Below I have included a screenshot of the LMK04828 tab in the ADC12DJ3200 EVM gui this is where you will have to configure the LMK04828 to pulser mode. The frequency of sysref will depend on your LMFC which can be calculated using the following equation 

f_sysref = SERDES_RATE / (10 * F * K *n ) 

This will be set using the sysref divider tab in the gui and will be based off the reference frequency given to the LMK.

Additionally you will have to make some hardware changes to the EVM board itself, for best performance I would DC couple sysref from the LMK to the ADC. Additionally if you wish to provide an external LMK reference you will have to make this swap as well. by uninstalling R67 and installing R70.

For your second question I am not sure exactly what you are referring too can you give some more clarification. If you are concerned with the SYSREF pulse happening before the ADCs are ready to configure SYSREF then you can trigger the SYSREF event to happen after the ADCs are done configuring and ready to receive a pulse.

Best,

Eric 

Thank you, Eric for quick response.

I changed the GUI configuration however, after programming, GUI configuration is changing to default automatically and there is no difference observed in SYSREF i.e SYSREF is continues pulse. Please see the attached snap.

Regarding second question, I am using FPGA as a receiver. FPGA programming and ADC programming time will be different. So how do I ensure that one shot pulse is not missed by the FPGA if FPGA programming time is more.

Thank you,

Krupesh

I am able to generate one shot SYSREF as per your suggestion if ADC and clock is not programmed after changing the SYSREF configuration (to run the warm/cold reset test, this is required). I would like to understand how to  program the SYSREF configuration changes. Also, after changing the SYSREF configuration, glitches are observed on SYSREF in my FPGA logic analyzer due to which both FPGA and ADC restart the operation. This may be due to DC coupling, you were suggesting. What exactly, I need to avoid this glitches? I don't want to use external clock for the LMK so as per my understanding, resistor replacement is not required on board.

Thank you,

Krupesh

Hello Krupesh,

Using the ADC GUI you have to program the ADC and clocks first using the button on the first page. Clicking this button is going to reset everything else in the GUI to default and you will have to do it all over again. 

To correctly get your ADC and FPGA aligned to sysref you must first program ADC, program FPGA, bringup FPGA link and then configure ADC sysref. One quick question can you confirm if you are using ti jesd ip, and what capture card you are using to capture data? Is it a TI solution, custom or other dev kit?

If you are trying to use pulser mode on the LMK you should DC couple the signal from the LMK to ADC and FPGA, I would also double check the sysref path on the FPGA to ensure it is not DC coupled somewhere there as well. I am not sure what you mean changing the SYSREF configuration, do you just mean changing the values in the GUI you see a glitch in the waveform or after you fire off an event?

Yes if you don't wish to use external clocks then you do not have to make any hardware changes.

Best,

Eric 

Hi Eric,

Please see my response below

Using the ADC GUI you have to program the ADC and clocks first using the button on the first page. Clicking this button is going to reset everything else in the GUI to default and you will have to do it all over again. 

To correctly get your ADC and FPGA aligned to sysref you must first program ADC, program FPGA, bringup FPGA link and then configure ADC sysref

Krupesh - Understanding is that automation is not possible i.e can not perform cold reset test as manually change the configuration for SYSREF after every power cycle. Understanding is that following steps should be followed in order to configure one short SYSREF.

(1) Power on the board

(2) Program ADC and Clock in the first tab

(3) Change the SYSREF configuration in LMK->SYSREF and SYNC tab and click on Trigger SYSREF button. 

One quick question can you confirm if you are using ti jesd ip, and what capture card you are using to capture data? Is it a TI solution, custom or other dev kit?

Krupesh - I am not using TI JESD IP. I am using other dev kit (Polarfire FPGA) to capture data

If you are trying to use pulser mode on the LMK you should DC couple the signal from the LMK to ADC and FPGA,

Krupesh - Can you please elaborate? Is there any configuration or hardware changes required in order to do DC coupling?

I am not sure what you mean changing the SYSREF configuration, do you just mean changing the values in the GUI you see a glitch in the waveform or after you fire off an event?

Krupesh -Yes. I closelly observed and figured out that glitch is not generated. SYSREF is toggled at regular time and remain asserted for more than one clock cycle. Understanding is that SYSREF shouldn't toggled in pulser mode until Trigger SYSREF button is clicked. Please see the attached configuration of SYSREF and debugger waveform (sysref_in is the input coming from ADC card).

Hello Eric,

Pulse shown in above waveform is not expected, right?As pulse count is set to 8 in SYSREF and SYNC tab of GUI, understanding is that when Trigger SYSREF is clicked, 8 pulses of SYSREF should be generated by LMK.

Am I missing anything in the GUI?

Hello Krupesh,

The procedure you have listed above is the correct procedure for configuring the ADC, clocks and sysref. If you require more advanced functionality I would suggest using a different approach from the gui to configure everything. The gui is more meant as a tool to evaluate the part and is not meant for more advanced use cases such as automated testing.

Yes there are some hardware changes to make to the board in order to enable DC coupling of sysref. As you can see in the screenshot below there are AC coupling capacitors on the line to the ADC from the LMK, you will have to replace these with a 0 ohm resistor. For the FPGA sysref is already DC coupled coming off of the ADC EVM so you will have to double check your FPGA board schematic and check that it is DC coupled and not AC coupled.

I see the signal you are mentioning in your ILA, I think this could be a sort of glitch coming out of the LMK when you change the configuration. Are you able to probe this signal with an oscilloscope and verify the waveform? 

Yes your understanding is correct, the pulse should not appear my thought is that there might be a large enough glitch on the sysref output to cause a logic High on your FPGA, but not a true sysref pulse is getting fired. And when you click fire sysref pulser it should output 8 pulses.

Best,

Eric Kleckner

Thank you, Eric for providing details for the hardware change. I will check FPGA board and make sure that it is DC coupled.

Can you suggest procedure to use continuous SYSREF (till pulser mode issue is fixed) for deterministic latency i.e considering different programming time of both ADC and FPGA? In order to test the deterministic latency, I have implemented one counter for pulser mode. Counter is reset when SYSREF rising edge is detected and increments by 1 after that till FPGA JESD IP gives first data i.e after completion of initialization and initial lane alignment. Expectation is that every power cycle, counter value should be consistent. I am using DEVICE_CLK coming from the LMK to increment the counter.

Hello Krupesh,

If your application is fine using continuous sysref then I would actually recommend using this instead of pulser mode as you will not have to DC couple sysref to any parts which can be a problem in some cases. 

First you should program the ADC and clocks on the first tab of the gui as you are already doing and then to configure continuous sysref in the gui you will go to the same spot in the GUI I have shown in my first post but instead of selecting the sysref source as pulser you will select continuous and then program the sysref divider to get the correct sysref frequency. Additionally, one thing I forgot to mention before was that you have to enable sysref output to the ADC as shown in the second picture.

Then once you have aligned sysref with the ADC and FPGA you can turn off the sysref outputs to the ADC and FPGA so you do not get any of the downside of running a continuous sysref in your system. This will be much simpler to implement then using sysref pulser I think as it will not require any hardware changes to the boards.

Best,

Eric

Thank you Eric. I will try the steps you provided to use continuous SYSREF.