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ADS127L11: ADS127L11 & SPI troubles

Part Number: ADS127L11

Hi,

I have an issue with communicating with the ADS127L11 converter. Connection:

  • 4-wire SPI,
  • external clock 25MHz,
  • SCLK about 12MHz,
  • START pin connected to GND,
  • RESET pin not connected.

Sequence of actions:

  • reset (0x8358),
  • wait 612us,
  • send 0x8510, 0x8620, 0x8793, 0x8888, 0x8300, 0x8302,
  • set CS=L (to see if the converter has started working),
  • wait for low state on SDO,
  • read STATUS (0x4200) to check if everything is OK.

The symptoms are that sometimes the converter does not start, and I have to repeat the entire sequence from the beginning. If it starts, sometimes the read status has CS_MODE=1 set. I repeat the entire sequence until everything is OK - the converter starts and there are pulses on SDO every 5.12us.

I wanted to hardware synchronize the measurement with the measured signal and changed the startup sequence (only start command) as follows:

  • CS=0, SDI=0, SCLK is working,
  • at the appropriate moment, I send 0x8302 and set CS=1.

The converter starts.

During tests, I repeat the entire procedure multiple times, and sometimes the converter starts in such a way that the results are every 4.99us (the correct time is 5.12us).

Are there any errors in SPI communication?

(As an example, I am attaching the sequence of the first two commands 0x8510 and 0x8620)

Best regards

Andrew

  • Hello Andrew,

    Welcome to the TI E2E community.

    I think you have signal integrity problems.  Although this may be a bandwidth limitation of your scope/scope setting/scope probe, the rise and fall times for SCLK and /CS are too slow.  Can you use a higher bandwidth setting on your scope to confirm the rising and falling edges of your signals measured at the ADC pins?

    When the ADC does start and occasionally updates at 4.99us, this indicates that the ADC is running from the internal oscillator, and did not switch over to your external 25MHz clock source.

    It does appear you are meeting timing requirements (other than rise and fall times), but I suggest adding a small delay between consecutive register writes, increasing the time that /CS is held high between operations.

    Also, if you do not have a good board layout with power supply bypass capacitors placed close to the device, this can also cause communications problems.  In addition, you may want to connect the RESET pin directly to IOVDD.  This is normally not required, but if there is a lot of noise coupling into this pin, it could cause problems as well.

    If none of the above suggestions help, and you confirm that the clock edges are much faster than shown in your attached plot, then I would need to see the schematic and board layout around the ADC to confirm if there are any hardware issues.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • Hello Keith,

    Thank you very much for the response. Indeed, at first I thought it was the limitations of my scope. However, as you mentioned, I remembered that I have series resistors of 200 ohms on all digital lines, and at these frequencies, that's definitely too much. I will change these resistors and see if it improves...

    Regards,
    Andrew
  • Hi Andrew,

    O.K., with 200Ohm resistors, this is likely the root cause.  Please let me know if this fixes your problem.

    Regards,
    Keith

  • Hi Keith,

    Yes, I changed resistors to 20ohm and now all commands execute correctly.

    Thank you again for your help Slight smile

    Regards

    Andrew

  • Hi Andrew,

    You are welcome!

    Regards,
    Keith