ADC3664: Sample rate and SLVDS frequency

Matth. B.

Part Number: ADC3664

Hi,

I have a question about table 9-3, 9-4 and 9-5 of the datasheet of ADC3664.

In each table, frequency of data is twice the dclk frequency but regarding timing diagram and because we are in DDR mode, my guess is that the frequency in MHz of the data is the same than DCLK in MHz but indeed the bit rate in MSPS would by twice the frequency DCLK.

Could you explain where I'm wrong, please?

Thanks

Best Regards

10 months ago

0 Geoff Roth 10 months ago

TI__Expert 4340 points

Hi,

Because the data is in DDR mode the data is sampled on the rising and falling edges of DCLK, so the data is twice the rate of the DCLK.

Regards,

Geoff

0 Matth. B. 10 months ago in reply to Geoff Roth

Expert 1145 points

Hello,

Yes but even if the rate of data is twice the rate of DCLK, the frequency in MHz is the same, no?

From fig 9-32 of ADC3664 datasheet :

Regards

0 Geoff Roth 10 months ago in reply to Matth. B.

TI__Expert 4340 points

Hi,

Yes, the frequency in MHz is the same.

Regards,

Geoff

0 Matth. B. 10 months ago in reply to Geoff Roth

Expert 1145 points

Ok, but in table in the datasheet,frequency between Data and Dclk is different so I'm asking.

Regards

+1 Geoff Roth 10 months ago in reply to Matth. B.

TI__Expert 4340 points

Hi,

Yes, the data should be in Mbps not MHz. We'll work to get it update in the datasheet.

Regards,

Geoff

0 Matth. B. 10 months ago in reply to Geoff Roth

Expert 1145 points

Hi,

Thanks for your answer.

Regards

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ADC3664: Sample rate and SLVDS frequency