Hi, team：
I have some question about TSC2004 test mode 0, could you help explain it:
1. I know if the power on slope not satisfied requirement will enter test mode, I want to know more detail what is the concrete power-on slope will enter, and how to judge the test mode.
2. In the table below, I can see that if I enter test mode, AD0 will be set to 0, and if I identify the device with the address of ad0=0, the chip will exit test mode, right?
Hi, Sanjay:
Thanks for your reply, we search document as follow in TI.COM. please let me more about the test mode0, due to currently we met I2C NACK issue when power up ramp is not satisfied the datasheet requiremet.
In Test Mode AD0 is set to 0.
If device pin AD0 is 0 then the software reset command shall bring device out of test mode automatically.
If AD0=1 then if the device has entered test mode it shall give no ack when device is adressed. Hence the device address needs to be changed to AD0 and then software reset be given
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If AD0=1 in the Hardware:
Write to I2C at device adress with AD1 as in pin config and AD0=1
10010 AD1 10
If No acknowledge is received then it is assumed that device has entered Test Mode due to improper device powerup sequence.
Now Set address as 10010AD100
Apply software reset as 10000010
The above table should be observed for a proper power on. Failute to follow this can lead to entry into test mode.
One way to enter test mode may be to wait for 10ms after supply has gone to zero and then start again
