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ADS131A04: Regarding ADC sampling jitter

jito
Prodigy 10 points
Part Number: ADS131A04

I am considering using the ADC evaluation board (ADS131A04EVM) to measure a 5kHz input signal with a sampling rate of 80kSPS or higher (for example, with a setting of 128kSPS).

I would like to measure the sampling jitter to be below 1ns. Does this evaluation board meet my requirements?

  • 0
    TI__Mastermind 48951 points

    Hi ?? ???,

    Is your question with respect to:

    • The channel phase to phase matching?
    • Or the clock jitter?

    The ADS131A04EVM has an external clock input that you can use to apply a very low jitter clock source if the crystal (Y1) introduces too much variation

    Let me know if this answers your question

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 10 points

    Thank you for your response. There was an error in the numbers. I am curious about whether, depending on factors such as (1) clock jitter, (2) the internal structure of the ADC, and (3) ADC communication control, the final sampling time will be within a range of +/- 10ns. If (1) clock jitter is a factor, I will use the external clock input that you mentioned. Are (2) and (3) sources of error? Even if there is an error, is it generally at a negligible level? If anyone knows, I would appreciate your guidance.

  • 0 in reply to jito
    TI__Mastermind 48951 points

    Hi jito,

    Can you please explain what you mean by "final sampling time"? Are you referring to the ADC conversion latency i.e. the time from when conversions begin to when data is ready? Are you referring to the time difference (phase delay) between ADC channels?

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 10 points

    I am sorry I didn't explain it clearly enough.
     

    Variability in ADC conversion latency is acceptable.
    I want to get the timing of ADC conversion correct.
    I didn't care about the time difference between the ADC channels because there are two converters in the hardware.How much is the time difference?

  • 0 in reply to jito
    TI__Mastermind 48951 points

    Hi jito,

    For an oversampling ADC such as the ADS131A04, the SNR impact due to jitter is given by the equation shown below

    If you want to run the ADC at 128 kSPS, the dynamic range if 85.12 dB and the OSR = 32. The 3dB BW is given by the plot shown below, which is ~1/4 of the data rate, or 32 kHz.

    Using this information and the equation shown below, you can calculate that to meet SNR_limit = 85.12 dB, you need t_jitter = 1.56 ns. However, you typically want to be 10-20dB higher compared to this value to make sure the clock jitter does not impact the measurement. At SNR_limit = 95.21 dB, you need t_jitter = 0.5 ns. This is the jitter required to have no impact on your input signal from the clock. If you increased the OSR (lowered the sample rate) or reduced the input frequency, then your jitter requirements would relax.

    -Bryan