• State Resolved
  • +1 person also asked this people also asked this
  • Locked Locked
  • Replies 11 replies
  • Answers 3 answers
  • Subscribers 47 subscribers
  • Views 238 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

ADC128S102: ADC128S102 Chip Select Monotonicity

ADC128S102: Nonmonotonicity Tolerance

Courtney Ballard
Prodigy 30 points
Part Number: ADC128S102

How tolerant is the SPI interface to nonmonotonicities? Is there a deglitch filter on the SCLK/CS/MOSI lines? I am seeing nonmonotonicities of up to 100mV and 0.5ns to 1ns on signal edges into the ADC, would these negatively affect the SPI communication?

  • 0
    TI__Expert 6791 points

    Hi Courtney,

    Thanks for your question. No such filters on the digital lines are mentioned in the datasheet. As long as the VIL and VIH and timing specifications are not violated, the SPI communication should be fine.

    As Collin mentioned in the original post, adding small resistors in series on these lines may help reduce any ringing.

    Best,

    Samiha

  • 0 in reply to Samiha Sharif
    Prodigy 30 points

    Changing the series terminations did not eliminate the nonmonotonicities, it just changed the voltage where they occur. There isn't ringing, just a single event likely due to a reflection which is occurring between VIH and VIL. Would it be possible to check with the factory about the deglitch filters? 

  • 0 in reply to Courtney Ballard
    TI__Expert 6791 points

    Hi Courtney,

    Could you please share a oscilloscope shot (with scale) of the ringing you are seeing on the digital lines?

    Best,

    Samiha

  • 0 in reply to Samiha Sharif
    Prodigy 30 points

    Here's an example of what we are seeing. There is a similar nonmonotonicity on the rising edge above the VIH voltage that is a lower concern:

  • 0 in reply to Courtney Ballard
    TI__Expert 6791 points

    Hi Courtney,

    Thanks for sharing. This should not pose any issues. Your SPI communications should be fine.

    Best,

    Samiha

  • 0 in reply to Samiha Sharif
    Prodigy 30 points

    Would you be able to provide any more detail as to why it should be okay? I'm glad if it is not an issue but I'd like more of an explanation if possible.

  • 0 in reply to Courtney Ballard
    TI__Expert 6791 points

    Hi Courtney,

    The event seems to be of 0.5ns-1ns duration and it is very small in amplitude. Looking at the timing specifications, this would not encroach on any of the timing requirements not violate the VIL/VIH specs.

    Best,

    Samiha

  • 0 in reply to Samiha Sharif
    Prodigy 30 points

    Which timing specifications do you mean? After reviewing this again, I agree that there are no concerns for nonmonotonicities (NM) on CS or DIN, only on SCLK. It is not clear what happens if there is a NM shorter than the minimum clock high/low time. As far as I am aware the setup and hold times are there to make sure the right value is read, but if the NM is seen as two clock cycles, then there would be an extra read regardless of the value. Is it the voltage amplitude or the short duration specifically that makes this not a concern, and how much margin is there? I don't know if the NM gets worse when tested over temperature, for example.

  • 0 in reply to Courtney Ballard
    TI__Expert 6791 points

    Hi Courtney,

    Could you share a scope-shot of SCLK so we can see the high and low times? My understanding is that if the NM is occurring on the SCLK edge, it is unlikely to affect the SCLK high/low times. I'm not sure what you mean by "if the NM is seen as two clock cycles", could you please elaborate?

    Best,

    Samiha

  • 0 in reply to Samiha Sharif
    Prodigy 30 points

    The datasheet says the minimum clock high/low time is 25ns, but it is not clear if SCLK changes shorter than that cause any issues. Taking the most extreme case for a falling edge, if the ADC sees high (actual) -> Low (NM) -> High (NM) -> Low (actual) much faster than the minimum SCLK high/low times, could that be seen as a very fast clock cycle?

    Here is a scope shot of the SCLK:

  • +1 in reply to Courtney Ballard
    TI__Expert 6791 points

    Hi Courtney,

    Thanks for sharing the scope-shot. The minimum high/low time is actually 18.75ns, as the minimum SCLK duty cycle is 30%, as shown below. Note: the datasheet formatting for these devices is a little confusing, 30% is the min duty cycle, 40%-60% is typical, 70% is max.

    So, unless the NM stays high or low for a minimum of 18.75ns (when using a 16MHz SCLK), the ADC will not recognize the NM as a SCLK cycle. As your NM is 0.5ns-1ns in duration, it should not pose a problem in SPI communication.

    Best,

    Samiha