ADS7953: PD的SCLK时序与SPEC不符

The test found that PD under the condition of DI05=1 would fall along PD at the 16th SCLK in the current frame, but not at the 16th SCLK PD in the next frame according to SPEC. Below, the first oscilloscope picture showed no PD success at the falling edge of 15 SCLK, while the second one achieved PD success at the falling edge of 16 SCLK

Hi,

What in the two pictures you provided shows that in one case the device did not power down while in the other it did?  What is the signal on the yellow trace (CH1)?

yes,yellow is cs,blue is sdi,red is sclk

OK - so what are you using as a definitive case for the device powered down?  I don't see that in the screen shots you provided.

the chip is in mannual mode,i send the sdi command with di05=1 to pd the device, not use gpio function,so find the VA'S current is 0 mA when the 16th sclk falling edge is coming in current frame

So in the first screen shot, yellow as /CS is not valid low for the first 3-4 SCLK cycles.  Can you fix that?

 this is the second picture

and the spec's description is inconsistent

From the last two screen shots, note how /CS (blue trace this time) is going high slightly ahead of the last SCLK, while in the second picture, there is maybe 200nS delay before /CS goes high.  Can you keep the /CS time constant observing at least tSU1 and tD3 timings (see page 17 of the datasheet)?

The device triggered PD,tD3 is 14ns,tSU1 is 10ns,and vbd is 3V.I want you to test it .Maybe this is a misinformation.