Other Parts Discussed in Thread: DAC8801, DAC8811,
Team,
Customer is reporting the following inconstitencies in the different datasheets.
Can you please comment?
1) DAC8801: In the data sheet https://www.ti.com/lit/gpn/dac8801 SLAS403B
-On page 9, the timing diagram (Figure 19) shows 15 instead of 14 clocks (for the data bits D13 to D0 and another unlabelled quasi D-1 bit).
However, as only the last 14 bits are valid according to the description, the D-1 bit shifts all transmitted data bits 1 bit to the left, i.e. D13 is omitted, D12 becomes D13, etc. D-1 becomes D0 and the transmitted data word is therefore transferred completely incorrectly and results in an incorrect output value. An example with 16 data bits, of which the first 2 are invalid as described in footnote (1) under Table 1 and the CLK signal after the D0 remains low, might be useful.
2) DAC8811: In the data sheet https://www.ti.com/lit/gpn/dac8811 SLAS411D
-On page 7, the clocks required to read the data bits DB15 to DB0 are correctly shown as 1 to 16. However, these are followed by a 17th L-H clock edge virtually at the same time as the CS signal is switched off. This should not be the case, because if the evaluation electronics of the CLK signal is slightly faster than that of the CS signal, a further data bit (D-1) is read in and all data bits read in so far are shifted 1 bit to the left and distort the output value (see 1) DAC8801). This means that the CS signal must become high half a cycle earlier or, even better, the CLK signal should remain high after the 16th cycle.
-On page 15, the caption "Figure 24. Data Input Register" is written differently than usual, confusingly above instead of below the picture.
-On page 15 in the figure "Figure 25 /CS Interrupt Facility", the CKL cycles shown do not match the Din data: There is no (valid) CLK edge at all for DB15, i.e. the first bit sent is ignored (DB14 becomes DB15) and at the end the 16th bit is missing and the data is not accepted - i.e. the second write sequence labelled "Valid" is also invalid! At least the /CS signal becomes high in time already at the H-L edge of the CLK signal (in contrast to the other timing diagrams of the 3 DACs).
3) DAC8812: In the data sheet https://www.ti.com/lit/gpn/dac8812 SBAS349F
-on page 6, the CLK clocks effective for reading in the data bits (A1, A0, DB15, ..., DB0) are incorrectly labelled 18 to 1 in the timing diagram (Figure 1) instead of 1 ... 18 in ascending chronological order (see DAC8811 1 ... 16). As with the DAC8811, a further L-H clock edge is also shown here, which coincides with the CS signal becoming invalid. This should not be the case, because if the evaluation electronics of the CLK signal is a touch faster than that of the CS signal, a further data bit (D-1) is read in and all data bits read in so far are shifted 1 bit to the left and falsify the output value (see 2) DAC8811). This means that the CS signal must become high half a cycle earlier or, even better, the CLK signal should remain high after the 18th cycle.
This is shown correctly in the competitor product AD5545.
-On page 16 in the Control Logic Truth Table (Table 2), I find the description "Transparent" as a property for the DAC register at /LDAC = L inappropriate. The DAC register is not transparent, but only in the case that /LDAC is at low level, the data from the input register is transferred to the DAC register and the new value is output. That's why I think the term "Updated" is much more appropriate than "Transparent".
Why are the tables labeled above and the images labeled below?
Thanks in advance,
Anthony
