ADS7028: In Manual mode, CHID incorrected

Yuki Kusakabe

Part Number: ADS7028

Hello, we are measuring analog voltages using CH0~CH2 of ADS7028.
We select manual mode and write CHID to the CHANNEL_SEL register. Set the APPEND_STATUS[1:0] bits of the DATA_CFG register to 01b and measure data with CHID.
In the experiment, When AIN2 was set to CHANNEL_SEL, and the data was measured two cycles later, the data for AIN0 was returned.
I will attach the waveform of the oscilloscope.

Is this a bug in the silicon, or is it because the CHID is not properly set due to some noise?
Could you please help me with my question?

8 months ago

0 Yuki Kusakabe 8 months ago

Prodigy 10 points

AIN0 -> AIN1
Figure is correct.

0 Tom Hendrick 8 months ago in reply to Yuki Kusakabe

TI__Guru**** 174456 points

Hi Yuke,

Welcome to our e2e forum! Can you please include the SCLK with your screen shot?

0 Yuki Kusakabe 8 months ago in reply to Tom Hendrick

Prodigy 10 points

Hi Tom,

Thanks for comment.

unfortunately, All spi signals not included.
ch1(yellow) is used for oscilloscope trigger when mismatched CHID detected.

but, The transmitted CHID and the returned data were the same as in the previous screenshot.

0 Tom Hendrick 8 months ago in reply to Yuki Kusakabe

TI__Guru**** 174456 points

Thank you Yuki,

Do you know what the cause of the noise on the SCLK is?

0 Yuki Kusakabe 8 months ago in reply to Tom Hendrick

Prodigy 10 points

Hi Tom

Tom Hendrick said:
Do you know what the cause of the noise on the SCLK is?

Yes, it's likely due to switching noise from the inverter.
The ADS7028 is measuring the voltage and current supplied to the inverter.
This noise is observed when the MOSFETs inside the inverter are switching.
Additionally, using a probe for measurements with an oscilloscope, connected using a ground lead, may amplify the noise.
Could the CLK noise be affecting the ADS7028?