The datasheet's Figure10 shows that the current increases as the sampling rate increases.However, the test found that in the power down mode, the current of the chip VA was very small. Even if the input clock speed was changed, it did not conform to the SPEC. It seemed that the analog part of the chip did not work.
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this is the signal input,and i test that the figure9 is normal.But i pd the device first and then capture data in the same way. i fund that the va's current closed to 0.The output code is zero. So it's seem that the annalog is not working.I wonder how figure10 was tested