Other Parts Discussed in Thread: LM98640QML-SP
Hi,
We are working with the LM98640QML-SP in a new design and also with the LM98640CVAL Evaluation Board.
The device is operating in S/H mode.
Gain is 2x (baseline value).
Inputs OS1+, OS1-, OS2+, OS2- are all DC coupled. (LM98640CVAL Eval Board default setup)
VCLP is set to 2.2Vdc (baseline value) and is connected to OS1+ and OS2+. (LM98640CVAL Eval Board default setup)
We program the registers with the baseline values first, and then we change the following registers:
We change LVDS mode register at addr 0x05 settings for Dual Channel operation (change from 0x0e to 0x06).
We change Clock Monitor register at addr 0x09 to enable monitoring DTM0 and DTM1 (change from 0x0 to 0x10).
We change INCLK Range register at addr 0x25 for 5MHz operation (change from 0x02 to 0x50).
We have tested with programming the reserved register at address 0x24 to a value of 0x34 but this seems to have no effect on functionality. (the support forum mentioned this)
We applied three different dc voltages to the OS1- input one at a time and looked at the TXOUT1 output signal.
We applied 1.29Vdc, 1.69Vdc and 1.97Vdc to OS1-. The TXOUT1 data was the same for each case.
For all 3 cases the TXOUT1 was outputting values of 0x1FE0 +/- 1 bit (0x1FDFor 0x1FE0 or 1x1FE1).
0x1FE0 corresponds to a value of 8160/16383 x 2v x 1/2x = 0.498V (assuming ADC reference voltage = 2V, Buffer gain = 2)
Why is the observed TXOUT1 signal not as expected?
Why do I get the same values on TXOUT1 regardless of input signal?
When the fixed voltage of 1.29Vdc was applied to the OS1- input we expected the following result.
OS1+ - OS1- = 2.2V - 1.29V = 0.91V.
The S/H buffer 2x gain increases the signal amplitude to 2 x 0.91V = 1.82V.
Assuming the Voltage reference for the ADC is 2V, the expected output on TXOUT1 would be:
(1.82v/2v) x 16384 = 14,909 dec = 0x3A3D hex
When the fixed voltage of 1.69Vdc was applied to the OS1- input we expected the following result.
OS1+ - OS1- = 2.2V - 1.69V = 0.51V.
The S/H buffer 2x gain increases the signal amplitude to 2 x 0.51V = 1.02V.
Assuming the Voltage reference for the ADC is 2V, the expected output on TXOUT1 would be:
(1.02v/2v) x 16384 = 8356 dec = 0x20A4 hex
When the fixed voltage of 1.97Vdc was applied to the OS1- input we expected the following result.
OS1+ - OS1- = 2.2V - 1.97V = 0.230V.
The S/H buffer 2x gain increases the signal amplitude to 2 x 0.230V = 0.460V.
Assuming the Voltage reference for the ADC is 2V, the expected output on TXOUT1 would be:
(0.46v/2v) x 16384 = 3768 dec = 0xEB8 hex
Are we calculating the expected outputs correctly?
Do I need to do any other changes from the register baseline values?
Programming reserved register at address 0x24 to a value of 0x34 had no effect on this functionality. Are there any other reserved registers that need to be setup?
We get similar results with our board and with the LM98640CVAL Evaluation Board.
We have oscilloscope and logic analyzer waveforms that we can share if that helps.
Thank you!
Scott Thomas
949-338-8463
