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ADS8506: About ADS8506 parallel data output timing

Part Number: ADS8506

It would be helpful if you could explain the following points regarding the ADS8506's parallel data output timing.

1) In Figure 34 of the data sheet, the time from the falling edge of CS until the data bus outputs High Byte is t21. The data sheet states the R/C setup time for CS, but is it correct?

2) If 1) is correct, the time from the falling edge of CS until the data bus outputs High Byte is a delay, so I think there should be a maximum value, but is there any information?

We apologize for the inconvenience, but it would be helpful if you could enlighten us.

  • Hello Yamada-san,

    Yes, there is delay for the BYTE transition on the databus.  You should use t12 as depicted in figure 33 and table 5 as the typical and maximum delay time for the transition.

  • Thank you for answering.

    According to Table 5, t12 is recognized as the data bus delay time for BYTE, but is it correct to understand that this value also applies to the data bus delay time for CS?

    Also, I apologize for asking multiple questions, but it would be helpful if you could provide information on the following two points.

    1) The data sheet says it is pin compatible with AD7806. Am I correct in understanding that this can be replaced with the AD7806?

    2) The AD7806 is a device that has been in production for over 30 years since 1992, although production of the AD7806UB continues. Is there any information regarding future production continuation?

    We apologize for the inconvenience and appreciate your understanding.

  • Yamada-san,

    The t12 reference is also the delay for the data bus (from the rising R/C input).  For your new questions:

    1.) Yes - they are pin and function compatible.

    2.) Please review our lifetime policy here: https://www.ti.com/support-quality/quality-policies-procedures/product-life-cycle.html