It would be helpful if you could explain the following points regarding the ADS8506's parallel data output timing.
1) In Figure 34 of the data sheet, the time from the falling edge of CS until the data bus outputs High Byte is t21. The data sheet states the R/C setup time for CS, but is it correct?
2) If 1) is correct, the time from the falling edge of CS until the data bus outputs High Byte is a delay, so I think there should be a maximum value, but is there any information?
We apologize for the inconvenience, but it would be helpful if you could enlighten us.