ADC12DL3200: Length matching across data lanes requirement

Hi Charan,

Technically no, you would not need to length match all four banks (ABCD) if you are using the two ADCs independently.

However, this might be a limitation with the type of FPGA you are using to capture the data. I am checking on this for you.

I will get back to you in a few days on this.

Regards,

Rob

Hi Charan,

Rob’s point is accurate (and you have mentioned this in your original post). Ideally, you don’t need to length match across AC and BD. 

That said, as each bus has its own clock and strobe pins, you need not match between A and C either. A buffer at the receive end should help you line up the samples after each bus has been captured independently. 

Regards,

Ameet 

Hi Ameet,

Thank you very much for the reply.

What should be minimum timing skew requirement between lanes A & C?

Also I need clarification regarding the following queries:

• As there is only 1 ADC in my design, I am not using SYSREF signal. But as per timing diagram in Figure 6-2. in Page 30, STROBE signal was getting asserted after detecting the SYSREF signal after tLAT(STB). If no SYSREF signal is being used, when does the STROBE signal be asserted? 
• If I am continuously capturing the data from ADC, does the STROBE signal gets asserted only once at the start or will it be toggled while capturing?

Thanks in advance  

Hi Charan,

The min timing skew is really up to how the Rx is determined. Meaning it’s about the setup/hold of the RX, not the TX.

There may be buffer settings within the FPGA in order to do this.

Otherwise, I would suggest no more than +/-100mils from diff pair to diff pair.

Ameet will address the rest of your questions.

Regards,

Rob

Hi Charan,

My recommendation will be to solve the A/C and B/D synchronization using the Rx architecture in the FPGA (instead of through timing closure and length matching constraints).

The ADC has a feature to group a certain number of samples into a frame. The STROBE signal serves to demarcate the frames from each other (which can then be used to align the outputs of multiple channels within an ADC or across multiple ADC's). The frame length can be set through the LFRAME regsiter (address 0x202). One common example is to set this to 16 (one strobe pulse every 16 samples).

Once you have the STROBE pattern, it will repeate indefinitely and you can use it to align the samples of A with C and B with D. This will help get around needing very tight routing restrictions (and hence easing board layout).

Finally, at high data rates, there is also a possibility of bit slips 'within' the lanes of a channel. The STROBE pattern can be used to your advantage here as well. The PAT_SEL register can be used to output the STROBE on all data and strobe lanes. This way, the Rx logic in the FPGA can align everything (lanes within a data bus as well as samples across data buses).

As a final point, the Xilinx HSSIO Rx IP should offer you a clean solution for bringing it all together. This will carry out the I/O calibration as well as inter-lane bitslip adjustment. Alternatively, you can implement your own logic to do the needful.

Kindly let me know if this addresses your queries.

Regards,

Ameet

Hi Ameet,

As you mentioned "As a final point, the Xilinx HSSIO Rx IP should offer you a clean solution for bringing it all together. This will carry out the I/O calibration as well as inter-lane bitslip adjustment. Alternatively, you can implement your own logic to do the needful." we are using HSSIO Rx IP.

As observed, 

1. Xilinx HSSIO Rx IP will not work on strobe basis. So, Is there any chance, that Strobe signal can be continuously low, until I complete my capture?
2. If not, How do I monitor strobe? Is detecting falling edge enough for starting the capture?

 Thanks in advance,

Charan.