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Problems about ADS58C48

Other Parts Discussed in Thread: THS4509, ADS58C48, ADS5517

Hi,

I am debugging a customized board. It's a high speed data acquisition card with THS4509+ADS58C48+FPGA.

The amplifier is THS4509 set as 20dB gain. And ADC is ADS58C48. Four channels are used. 200MHz. LVDS is employed.

 

Current problem:

The output of ADC is not correct. There are lots of glitches generated by the ADC rather than the actual input signal. And the ADC cannot convert the input signal correctly.

 

The ADC output data captured by FPGA is shown as follow:

S_ad_1buf[2] is the third channel of ADC. The input of this channel is a five cycles sine waveform. But it's not correct.

There is no input of other channel, but the output of ADC has large amplitude glitches.

Oscilloscope picture about the ch-6 of the third channel of ADC, there is no input of ADC, but glitches exist in the output of ADC.

 

Debug:

The communication between ADC and FPGA is OK. The ADC registers can be configured correctly. The testpatter 010101 could be generated and acquired by the FPGA properly.

 

The testpattern data could be generated and acquired correctly shows both the ADC and FPGA worked normally.

But when switch the ADC to normal operation, the glitches occured and the data cannot be convert correctly.

I assume the reason maybe cause by the driver: THS4509 since the normal drive method is a transformer which is shown in the datasheet.

I have tried to adjust some configuration of THS4509, no improvement. 

I don't think the THS4509 cannot be used to drive the ADC. The schematic is shown for reference.

 

It's highly appreciate if the specialist in TI could help me to solve this problem. Thanks

Regards,

Derek

 

 

 

  •  

     

    Hi,
     
    I just launched another test using the digital pattern test in the ADC.
    100 Outputs digital pattern, Output data increments by one LSB (11-bit) every 8th clock cycle from code 0 to code 2047
     
    There are something wrong with the test. The attached picture shows the problem.
    The odd data is not synchronized with even data periodicly.
    Maybe the former problem is caused by this.
     
    But I don't how to solve it. I try to change the register 0x42 to adjust the clkout.
    The output changed irregularly however.
     
    Can anyone give me some suggestion in this issue?
     
    Thanks
     
    Best regards,
    Derek
  • Hi,

    I suspect you have the clock polarity used to capture the DDR data into an input DDR cell inverted, or else if the IDDR cell has options to add an extra pipeline delay to either odd or even data that you are not accounting for it correctly.  For example, the Xilinx IDDR cell (after catching data on rising edge and falling edge and realigning falling edge data to the rising edge) has an option to add another stage to the rising edge data.  You may have an option like this enabled and not account for it, or vice versa.

    I think this is also apparent in the first few data captures that you showed where the idle channel noise (no input signal) has a little offset and occasionally crosses midscale to go from 100 0000 00xx to 011 1111 11xx and you can see that the '1111's are not all aigned up either.

    Regards,

    Richard P.

  • Dear Richard,

    Thanks for you instruction, the problem is solved.

    As you said, it's a problem in the FPGA since the rising edge and falling edge of clock is not synchronized.

    And also the data should be buffered at least for one clock otherwise the data will be shifted. The former "problem" will be emerged.

     

    One thing need to be mentioned, the FPGA should use different clock strategies to treat the DDR LVDS data in terms of ADS5517 and ADS58C48.

    Maybe rising edge of clock for odd data, falling edge clock for even data. It's different between ADS5517 and ADS58C48.

     

    Thanks again for your help.

    Best wishes,

    Derek