AFE5816: Required clock at AFE5816 & test patterns

Koo SeongWoo

Prodigy 120 points

Part Number: AFE5816

Hi everyone,

I have two questions about AFE5816

1) Absolute maximum of ADC_CLK (single-ended case & LVDS case)

2) Does the test pattern in AFE5816 operate independently of the ADC clock?

Thanks

over 1 year ago

0 Koo SeongWoo over 1 year ago

Prodigy 120 points

Additionaly, Can i get a information about Vih(high-level input voltage) and Vil(low-level input voltage) of ADC_CLK??

+1 Sachin H K over 1 year ago

TI__Expert 6565 points

1) ADC_CLK - LVDS mode - standard LVDS swing is 350mVpp. When you apply from outside to device 700mvpp you are 350mvpp . So maximum is 450mvpp according to lvds standard . So you can apply 900mVpp in LVDS mode .

In CMOD mode better to be within 1..9Vpp

2) You need ADC clock to get the test pattern

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AFE5816: Required clock at AFE5816 & test patterns