ADS8664: SPI Communication

Troy Sims

Prodigy 20 points

Part Number: ADS8664

I am trying to interface to the ADS8664 chip with SPI communication, but I am running into errors.

This is the schematic that I am using.

I am trying to enable channel 0, 1, and 2 for AUTO_SEQ.

So, I am sending 0x0307. Address for AUTO_SEQ_EN [000001] WRITE [1] and the data [00000111].

I then read back the data written to the register, which should be [00000111]. I believe that I am getting the correct response but I am unable to read it due to the variation in the rise and fall times. Or, the response is [00000110] which I am unsure why it would be that.

Red = CS

Yellow = SDI

Green = SDO

Blue = SCLK

The rising and falling plot of SDO. You can see that it is inconsistent and I only have 10 ns resolution (100 MHz clock on FPGA).

I hope that the plots are clear. Let me know what I am doing wrong or if you need more information.

8 months ago

0 Tom Hendrick 8 months ago

TI__Guru**** 175111 points

Hi Troy,

Can you re-take the screen shot of your SPI command with the traces separated a bit? SDI and SDO are a little hard to make out with the color scheme. For the individual bit transition, can you grab a few more clock cycles and ideally a data-bit transition.

0 Troy Sims 8 months ago in reply to Tom Hendrick

Prodigy 20 points

SDI & SCK:

SDO & SCK:

SDO (Data Transition) & SCK:

Hopefully this helps, let me know if you need any other photos of the signal.

+1 Tom Hendrick 8 months ago in reply to Troy Sims

TI__Guru**** 175111 points

Hi Troy,

Thank you for the additional pictures! Is that last one your SDO? Is it possible for you to speed up the sclk? Can you try the same thing with say 5MHz SCLK?

0 Troy Sims 8 months ago in reply to Tom Hendrick

Prodigy 20 points

Yes, the last one is the SDO. I can speed up the SCLK. The previous photos the SCLK was @1MHz.

5 MHz SCLK are below.

SDI (SCLK @5MHz):

SDO (SCLK @5MHz):

SDO (data transition) (SCLK @5MHz):

0 Tom Hendrick 8 months ago in reply to Troy Sims

TI__Guru**** 175111 points

Knurly clock there, but it looks like you are getting 0x07 on SDO. Is there anything you can do to speed up the SCLK edges?

0 Troy Sims 8 months ago in reply to Tom Hendrick

Prodigy 20 points

Here is the SDI & SDO without probing the clock and the signal is not as crazy. Nothing that I can think of, I'm outputting the clock from an Arty A7 FPGA dev board through the PMOD connector and doing LVCMOS33.

0 Tom Hendrick 8 months ago in reply to Troy Sims

TI__Guru**** 175111 points

That does look better. The SDO should be valid on the falling SCLK - it will look like the SPI phasing is off since the SDO clocks out with only 10nS of hold time, but CPOL=0 and CPHA=1 (SPI Mode 1) is how you should be operating the device.

0 Troy Sims 8 months ago in reply to Tom Hendrick

Prodigy 20 points

Sounds good thank you! Got it working now. Just needed to operate it at 5 MHz and adjust some FPGA code.

Thanks!

0 Tom Hendrick 8 months ago in reply to Troy Sims

TI__Guru**** 175111 points

Cool! Glad to hear that you have it working!

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ADS8664: SPI Communication