Hi,
We are looking at a design to simultaneously sample from at least 3x ADS9224R and grab the data from all 6 channels over the UPP interface on the F28379D. The goal is to achieve higher than 500 ksps for all 6 channels.
Note1: I'm aware UPP is not going to be present in future TI developments, and this is acceptable to us.
Note2: Using the internal ADCs on the F28379D for this function is not feasible.
My approach is the following:
1) Tie all the CONVST inputs of the ADS9224R together so the conversion start happens at the same time for all the ADCs.
2) Using the Zone 2 data read method over the parallel interface, have the DSP set the nCS pin on the ADC#1 and receive all the transmitted data from ADC #1. Once all this data is received, bring nCS#1 high and then bring nCS#2 low to read the data from ADC#2, get the data, and then repeat the process for ADC #3.
3) Therefore, after 10.5 CLK cycles + some delay, I should have data from 6 simultaneously sampled channels that can be processed. Please correct me if that conclusion is wrong.
On to my question, and I believe this is only relevant for Zone 2: The datasheet for the ADS9224R states the tD_CONVST_CS is "Delay time: CONVST high to CS falling for zone 2 transfer" and I take this to mean I can't bring the CS pin low for at least 180 ns after bringing CONVST high. On the flip side, is there a maximum time in which the CS pin must be brought low in order to begin the data transfer?
For example, let's say 2µs elapses before nCS is brought low. Is this acceptable in the eyes of the ADS9224R? It seems reasonable to me that this is the case, but if not then I need to rethink my approach for this design.
Regards,
B