Hello,
I am working with the ADS9224 ADC and I have questions regarding the interface and timing of Zone 2. Is the 3Msample/second rate defined for Zone 2? t_DRDY = 315ns must be the max conversion time. In zone 2, we always read the previous sample. Therefore, at the end of the current data transfer, the data from the previous conversion is available for the next 315ns. It should be available even before we assert the CONVST line (we cannot assert CONVST more often than each 333ns). My guess is that the CONVST assertion during Zone 2 causes the buffer to be copied from the internal ADC register to the SPI output buffer, and this takes up to tD_CONVST_CS (min) time == 15ns. Are these assumptions correct? Also according to the note on optimum performance with zone 2 transfer, [tD_CONVST_CS + tREAD] must be kept below 150 ns. Why is 150 ns the limit and not something closer to 333 ns? What is the max time for [tD_CONVST_CS + tREAD]?