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ADS9224R: Interface / Timing Questions

Part Number: ADS9224R

Hello,

I am working with the ADS9224 ADC and I have questions regarding the interface and timing of Zone 2. Is the 3Msample/second rate defined for Zone 2?  t_DRDY = 315ns must be the max conversion time. In zone 2, we always read the previous sample. Therefore, at the end of the current data transfer, the data from the previous conversion is available for the next 315ns. It should be available even before we assert the CONVST line (we cannot assert CONVST more often than each 333ns). My guess is that the CONVST assertion during Zone 2 causes the buffer to be copied from the internal ADC register to the SPI output buffer, and this takes up to tD_CONVST_CS (min) time == 15ns. Are these assumptions correct? Also according to the note on optimum performance with zone 2 transfer, [tD_CONVST_CS + tREAD] must be kept below 150 ns. Why is 150 ns the limit and not something closer to 333 ns? What is the max time for [tD_CONVST_CS + tREAD]?

I would also like to verify that Figure 36 of the datasheet showing an internal oscillator not connected to any external signals (except AVdd) means that conversion is independent of SPI CLK, and measurement accuracy will not be affected by any instability in the SPI CLK.
Thank you
  • Hello Jesus,

     

    3MSPS for can be used for both zones.

    To address some of the questions and assumptions in the 1st paragraph I wanted to go over some of the differences and similarities of zone 1 and 2.

    In both modes bringing CONVST high is what begins the conversion of Sample N, pulling CS down is what begins the read process. In zone 1 the output pin READY is used to indicate that the data is ready and can be read by the host. In this mode tD_CONVST_CS-min should align with tDRDY to make use of the 0 latency of the mode, bringing CS low (when meeting the timing requirements) will allow you to read sample N within the same frame. This also makes tDRDY max of 315ns only relevant in zone 1.

    Zone 2 has a latency of 1 to allow for a longer read time, so the READY output is not required. CONVST still triggers the conversion of sample N in this mode, but the timing of CS being pulled low is not dependent on the READY output. The tD_CONVST_CS limits specified in the timing requirements for this zone still have to be followed though. This due to the output being sample N-1 and that conversion being completed in a previous frame.

    You are correct, the data for sample N should be converted and ready before the adjacent CONVST is asserted again, and yes, in order to assert this again the minimum 333ns between adjacent CONVST needs to be met for this to happen. But the 315ns limit you are referring to does not apply in zone 2, sample N will be readable in the adjacent frame, if all the timing requirements for the mode and protocol are followed.

    As far as the note, it is referring to how the use of the enhanced SPI protocols available in this device can be used for an optimum performance that could allow for tD_CONVST_CS+ tREAD be below 150ns. The limit for tD_CONVST_CS is shared above (15ns to 180ns) and the tREAD timings are specified in the “7.6.2.1 Protocols for Reading From the Device” section. For example, the Legacy SPI:

    If using the max fCLK for single data rate (60MHz), and the minimum setup and delay timings for CS/SCLK edges, tREAD~=284.3ns, adding tD_CONVST_CS to it gives you somewhere between ~300ns to ~460ns.

    If you read through the section you can find that in the best-case scenarios if you use a quad SDO or parallel bytes you can get your tREAD to be 100ns or less, making the suggested “below 150ns” possible.

    This does leave the max spec open and I can see how that could be confusing, I will give this as feedback for the datasheet. Thank you for bringing it up to our attention.

     

    Lastly for figure 36, yes, the internal clock is independent of the SPI CLK.

    Best regards, 

    Yolanda

  • Hello Yolanda, 

    Thank you for your response, it clears it up for me. 

    Just a comment on why I assumed 3MSPS is only for Zone 2. 

    If in Zone 1 tDRDY max = 315, then even with protocol SPI-x1-Q_DDR (tREAD =[3 * tCLK + k]) and fCLK = 60MHz, we only achieve ~2.55 MSPS. Do we just count on tDRDY being less than 315 ns?

    Thank you, 

    Jesus