I am trying to verify the output from the AFE using a test pattern. I want to check the output data through ILA, and the clocks are as follows: ILA clock = 280MHz AFE input clock = 10MHz It is set to 14bit 1X serialization.
In the toggle pattern, as in the datasheet, we can see that the data changes at the center of DCLK. However, in the ramp and sync, some of the data was observed to change at the edge of DCLK. What could be the potential problem and solution?
1) SYNC pattern (works wrong)
2) Toggle pattern (works well)
3) RAMP pattern (works wrong)
I checked my supply voltage and ADC_CLK
Supply voltage is fine and also ADC_CLK looks fine (figure below)
These are my Register setting values.
Hardware reset
Register 1 , Value 14
100us wait
Register 41 , Value 8000
Register 42 , Value 8000
100us wait
Register 41 , Value 0000
Register 42 , Value 0000
Register 3 , Value 2010
Register 4 , Value 0001
Is there any solution or potential problems?
Thank you
