We are attempting to improve the INL performance of the ADC3683 by using code correction techniques. In our measurements we generally see a greater INL magnitude than reported as typical in the ADC3683 datasheet and also variance of at least +/-4 LSB in the INL characteristic between test runs, although at the moment we issue a software reset at the start of each test run. We are using the EVM balun input to generate our INL plots with high order ADC testing filters and sinusoidal excitation. Sample clock is generated from a high performance clock source. This has raised a number of questions about the behaviour of the ADC3683.
A typical INL result we have measured is:
After power cycling though we have the following diff between a new INL measurement and the measurement above:
1) Was this figure on page 24 of the datasheet produced using the EVM circuit (which includes baluns that add some non-linearity) or was a special circuit used?
2) Is the ADC power up calibration expected to yield the same INL characteristic each startup? (I.E is it deterministic)
"Apply hardware reset. After hardware reset is released, the default registers are loaded from internal fuses
and the internal power up capacitor calibration is initiated. The calibration takes approximately 200000 clock
cycles." P.G 72
3) Does a software reset (write to REG 0x0) trigger the calibration routine or is this only triggered by hardware reset?
