Team,
We want to check with you about the DAC904’s CLK input design requirements. If we use 122.88Mhz LVPECL’s single end as input, is that okay?
Thanks
Qiang
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Team,
We want to check with you about the DAC904’s CLK input design requirements. If we use 122.88Mhz LVPECL’s single end as input, is that okay?
Thanks
Qiang
Qiang,
No, it doesn't have enough swing to cover the VIH and VIL requirements in either of the supply modes. They will need a translator from LVPECL to LVCMOS/CMOS.
Regards,
Geoff
Geoff,
So the 3.3V LVTTL can also meet the design requirement? Thanks!
Regards,
Qiang
Qiang,
If the customer has the supply set to 3.3V then a LVTTL signal of 3.3V will work.
Regards,
Geoff