ADC12DJ3200EVM: Query regarding configuring ADC for 2.5Gbps data rate per lane

Krupesh Patel

Part Number: ADC12DJ3200EVM

Hi,

I am using ADC12DJ3200EVM and Microchip FPGA board to verify the functionality of JESD204BIP of Microchip. I want to operate ADC on 2.5Gbps data rate per lane and I am configuring JMODE - 3 and Fs = 1250 as shown in the below snapshots. Understanding is that , for this configuration ADC12DJ3200EVM generates 62.5MHz DEVICE_CLK for the FPGA. Is this understanding and configuration is correct?

4 months ago

0 Eric Kleckner 4 months ago

TI__Expert 4250 points

Hello Krupesh,

Yes this understanding is correct.

Best,

Eric

0 Krupesh Patel 4 months ago in reply to Eric Kleckner

Prodigy 20 points

Thank you, Eric for the confirmation. I am using only 4 lanes in FPGA (even though 8 lane is configured in JMOD -3), it is observed that data coming on each lane have huge skew (1000 clock cycle ) which violates JESD204B LMFC boundary requirement to release the buffer. Functionality wise there is no issue observed. Any thoughts in this issue?

0 Geoff Roth 4 months ago in reply to Krupesh Patel

TI__Expert 3370 points

Krupesh,

Can you tell me what project you are working on b/c Microchip is a direct competitor of TI in some spaces.

Regards,

Geoff

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ADC12DJ3200EVM: Query regarding configuring ADC for 2.5Gbps data rate per lane