Hi,
I have encountered a problem while working with ADS62P29. My application consists of THS4509 amplifier, ADS62P29 ADC and Spartan 6 FPGA. ADC is sampling baseband signal (0-15 MHz) with 160 Msps rate, connection to FPGA is in LVDS mode, ADC is clocked from Analog's ADF4350.
I noticed that once for 10^10 to 10^11 samples data from ADC has errorneous bit D8. It happens once in channel A, the other time in channel B and it appears in the same way on different boards. The error comes from inside of ADC - below you can see data from FPGA input downloaded to Excel chart and analog view of ADC input. The spike can be clearly seen at the FPGA input. I also checked digital LVDS lines bit-by-bit and the error appears already on ADC digital outputs (see third picture - there should be '1' in the center).
I tried different R-C-R circuits at the ADC input (but I don't think that matters - the ADC input waveform is taken from ADC pins), different clocking amplitudes (now it's 0.7V pp), I also tested ADC-FPGA communication using test patterns (both alternating values and digital ramp - both worked correctly up to 250 Msps) and lower sampling rates (137.5 MHz is the least I can get from ADF4350). And it's always bit D8.
Any ideas what happens here? How can I fix that?
Piotr
