ADC12DJ5200RF: JESD pattern maximum length

David Park

Part Number: ADC12DJ5200RF
Other Parts Discussed in Thread: DAC39RF10,

Tool/software:

Hi,

Customer would like to adopt 5u of ADC12DJ5200RF and 5u of DAC39RF10.

To mount these all components, pattern length is over 100mm.

Could you let me know what is maximum length for JESD lane from data converter to FPGA?

Please guide layout for this requirement.

Thanks.

0 Geoff Roth 6 months ago

David,

We need more specifics.

1) What is the data rate will the customer will use the SERDES at b/c this will determine how far it can drive/receive?

2) What type of board material is the customer using?

3) Are the traces external (microstrip) or internal (stripeline)?

Regards,

Geoff

0 David Park 6 months ago in reply to Geoff Roth

Hi Geoff,

Please refer below.

1. Data rate : 6Gbps-10Gbps
2. Board material : Megtron 6
3. Traces : Stripeline

Thanks.

0 Geoff Roth 6 months ago in reply to David Park

David,

100mm shouldn't be an issue as long as high-speed digital routing practices are followed.

Regards,

Geoff

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