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DAC80508: Need clarity on Daisy Chained Operation, Possible error in Data Sheet

Part Number: DAC80508

Tool/software:

Hello,

We are trying to optimise our design which requires 16 DAC channels to have a synchronised output and we are currently evaluating a solution that consists of two DAC80508 connected in Daisy Chain mode. 

While we plan to use Boradcast Value in the Register maps to simultaneously update ALL 8 channels, we want to determine if the same is possible for us to do on all 16 channels of two DACs connected in Daisy chain, our queries are,

1) In the data sheet, it seems like all CS pins had to be connected in parallel to a single GPIO? It seems like its an error in the graphics on the data sheet as all CS are terminated at a node however they're not connected.

If the graphics is accurate, and in case if all CS require their dedicated GPIO, how is the CS handled in that case?

2) If we put DAC in write mode and then write a value in both Broadcast Registers of Both DACs respectively, do you think all outputs will update simultaneously on the CS edge? This considers both devices have the CS pins connected in parallel. 

3) I think that the transfer speed of SPI will be halved if the CS is common, am I right in my assumption?

  • Hi Manas,

    The "Daisy-Chain Operation" section on page 25 of the datasheet explains how daisy chaining works for the DAC80508. In this case, all CS of the devices are shared. You will need to send 48 clock signals, where the first 24 clock signals communicates to device "A" in the figure, and the last 24 cycles communicates to device B. You will effectively be sending the same command twice while keeping CS low for both commands. 

    Due to sharing a CS, both devices will update at the same time. Since you will be doubling the amount of clock signals to write to both devices, the transfer speed will functionally be halved.

    Let me know if you have any other questions.

    Thanks,
    Erin