Tool/software:
If we start pulsing /RD after the BUSY goes low, but /CS goes low a little later, after some /RD pulses have already been made (let's say 2). Will the data on the parallel bus for the 3rd /RD pulse (first with /CS low) be for A0 or for B0?
Hello Rotero,
Thank you for the interesting question. There are two things to consider here, that /RD enables the data output if /CS =0. In the timing requirements there is also tBUCS to consider, which designates the minimum time delay between BUSY low transition and CS low transition, meaning that the valid data will be available after that requirement is met. Following this the data on the 3rd /RD pulse and the 1st /CS pulse should be for A0.
Best regards,
Yolanda
