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ADS8671: There are some questions

Atsushi Hirai
Expert 4290 points
Part Number: ADS8671

Tool/software:

Hi team,

I received some questions about ADS8671 from customer. Please support.

1) Datasheet parameter tD_RST_APP is speced 1us max. Does it mean CONVST/CS must be toggled Low to High within 1us after the rising edge of RST for proper reset operation?

Is it okay that we toggle CONVST/CS together with RST or earlier than RST?

2) Customer is going to use this device like below diagram. It repeats short Low pulse for conversion trigger(SCLK stay low) and Output data read(SCLK has only 8 cycles to read out 14bit data by Dual SDO-x mode).

What is the minimum pulse width for CS?

If the High period after the short pulse is enough longer than tconv, customer can read out ADC Data(N), ADC Data(N+2) as their expectation. Is it correct?

Best Regards,

  • 0
    TI__Guru**** 175111 points

    Hi Hirai-san,

    For point 1, please refer to the second bullet point of section 7.4.2.1 - the 1uS delay is for allowing time to do a complete power-on reset of the device.  Assertion of CONVST/CS needs to wait until after the MAX time elapses.  There is no need to continuously toggle RST, so tying that pin to CONVST is not recommended.

    For point 2, please review the various timing diagrams in section 6-11.  The /CS low time would be the 'Data Read Time' which is going to be dependent on your SCLK frequency and whatever minimum delays there are for the initial setup times (i.e. tSU_SCLK).

  • 0 in reply to Tom Hendrick
    TI__Expert 4290 points

    Tom-san,

    For point 1, I've understood the 1us max spec is reset period, and CONVST/CS must be toggled Low to High at least 1us after the rising edge of RST for proper reset. Please let me know if my understanding is incorrect.

    For point 2, you don't understand customer's question correctly. N and N+2 are short Low pulse for triggering a conversion.

    There is no SCLK signal during N and N+2 period. Is it okay?

    Conversion is started as their expectation?

    Is there a requirement for the low period to start conversion?

    ADC Data(N) can be read at N+1 period by this sequence?

     

    Best Regards,

  • +1 in reply to Atsushi Hirai
    TI__Guru**** 175111 points

    N and N+2 are the CONVST functions (not /CS), and they do not need an SCLK.  However, the rising CONVST/CS will trigger a new conversion cycle.  You have to wait until the internal conversion is complete before re-starting N+2.  This is not the conventional way to run the ADS8671, so there is no datasheet specification for a minimum /CS low time.  Consider 100nS pulse as a guideline.