ADS1299: ADS1299 SPI clock rate issue

Gaston Schelotto

Part Number: ADS1299

Tool/software:

Hello,

I've managed to communicate to my ADS1299 custom board successfully. The problem is it limited to 5MHZ SPI clock rate. More than this results in unsuccessful writing and reading ADS1299 registers.

I perform the required POR and RESET sequence after Power Up
Set the SPI timing as suggested in the ADS1299 datasheet
I've checked the SPI bus with my 200MHz oscilloscope and every seems correct.

Has anyone else run into this problem?

Why might this happen? How can I set a successful communication at 8MHz SPI clock rate?

Thanks in advance,
Gaston

11 months ago

0 Ryan Andrews 11 months ago

TI__Guru 64976 points

Hello Gaston,

Thank you for your post.

The SCLK frequency is limited to 20 MHz for DVDD > 2.7 V. However, for multi-byte commands like RREG and WREG, there is another limit known as "tSDECODE", which specifies the minimum amount of time each byte must take to transmit. This limit is 4*tCLK, or 1.96 us, assuming the default clock frequency of 2.048 MHz. In other words, if SCLK is greater than or equal to 2x the CLK frequency, a delay must be added between bytes.

Please check our BIOFAQ for more details about this topic as well as other helpful FAQ posts related to the ADS129x device family.

[FAQ] ADS129x: What is the minimum frequency for my SCLK? - Data converters forum - Data converters - TI E2E support forums

Regards,

Ryan